KW41Z datasheet(30/91 Pages) NXP

30 / 91 page

Depending on the stop requirements of the user application, a variety of stop modes are

available that provide state retention, partial power down or full power down of certain

logic and/or memory. I/O states are held in all modes of operation. The following table

compares the various power modes available.

For each run mode there is a corresponding wait and stop mode. Wait modes are similar

to ARM sleep modes. Stop modes (VLPS, STOP) are similar to ARM sleep deep mode.

The very low power run (VLPR) operating mode can drastically reduce runtime power

when the maximum bus frequency is not required to handle the application needs.

The three primary modes of operation are run, wait and stop. The WFI instruction

invokes either wait or stop depending on the SLEEPDEEP bit in Cortex-M0+ System

Control Register. The primary modes are augmented in a number of ways to provide

lower power based on application needs.

Table 9. Power modes (At 25 deg C)

Power mode

Description

CPU

recovery

method

Radio

Normal Run (all

peripherals clock off)

Allows maximum performance of chip.

—

Radio can be active

Normal Wait - via WFI Allows peripherals to function, while allowing CPU to

go to sleep reducing power.

Interrupt

Normal Stop - via

WFI

Places chip in static state. Lowest power mode that

retains all registers while maintaining LVD protection.

Interrupt

PStop2 (Partial Stop

Core and system clocks are gated. Bus clock

remains active. Masters and slaves clocked by bus

clock remain in Run or VLPRun mode. The clock

generators in MCG and the on-chip regulator in the

PMC also remain in Run or VLPRun mode.

Interrupt

PStop1 (Partial Stop

Core, system clocks and bus clock are gated. All bus

masters and slaves enter Stop mode. The clock

generators in MCG and the on-chip regulator in the

PMC also remain in Run or VLPRun mode.

Interrupt

VLPR (Very Low

Power Run) (all

peripherals off)

Reduced frequency (1MHz) Flash access mode,

regulator in low power mode, LVD off. Internal

oscillator can provide low power 4 MHz source for

core. (Values @2MHz core/ 1MHz bus and flash,

module off, execution from flash).

Biasing is disabled when DC-DC is configured for

continuous mode in VLPR/W

—

Radio operation is possible

only when DC-DC is

configured for continuous

mode.1 However, there may

be insufficient MIPS with a

4MHz MCU to support much

in the way of radio operation.

VLPW (Very Low

Power Wait) - via WFI

(all peripherals off)

Similar to VLPR, with CPU in sleep to further reduce

power. (Values @4MHz core/ 1MHz bus, module off)

Biasing is disabled when DC-DC is configured for

continous mode in VLPR/W

Interrupt

Table continues on the next page...

System and Power Management

MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018

NXP Semiconductors

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