KW41Z datasheet(68/91 Pages) NXP

68 / 91 page

7.5.8.1 DSPI switching specifications (limited voltage range)

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with

master and slave operations. Many of the transfer attributes are programmable. The

tables below provide DSPI timing characteristics for classic SPI timing modes. See the

DSPI chapter of the Reference Manual for information on the modified transfer formats

used for communicating with slower peripheral devices.

Table 41. Master mode DSPI timing (limited voltage range)

Num

Description

Min.

Max.

Unit

Notes

Operating voltage

2.7

3.6

Frequency of operation

—

MHz

DS1

DSPI_SCK output cycle time

2 x tBUS

—

DS2

DSPI_SCK output high/low time

(tSCK/2) − 2 (tSCK/2) + 2

DS3

DSPI_PCSn valid to DSPI_SCK delay

(tBUS x 2) −

—

DS4

DSPI_SCK to DSPI_PCSn invalid delay

(tBUS x 2) −

—

DS5

DSPI_SCK to DSPI_SOUT valid

—

8.5

DS6

DSPI_SCK to DSPI_SOUT invalid

-2

—

DS7

DSPI_SIN to DSPI_SCK input setup

16.2

—

DS8

DSPI_SCK to DSPI_SIN input hold

—

1. The delay is programmable in SPIx_CTARn[PCSSCK] and SPIx_CTARn[CSSCK].

2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

DS3

DS4

DS1

DS2

DS7

DS8

First data

Last data

DS5

First data

Data

Last data

DS6

Data

SPI_PCSn

SPI_SCK

(CPOL=0)

SPI_SIN

SPI_SOUT

Figure 13. DSPI classic SPI timing — master mode

Table 42. Slave mode DSPI timing (limited voltage range)

Num

Description

Min.

Max.

Unit

Operating voltage

2.7

3.6

Frequency of operation

MHz

Table continues on the next page...

MCU Electrical Characteristics

MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018

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