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AD9557 Datasheet(PDF) 39 Page - Analog Devices |
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AD9557 Datasheet(HTML) 39 Page - Analog Devices |
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39 / 95 page  Data Sheet AD9557 Rev. C | Page 39 of 95 The APLL lock detect signal gates the sync signal from the channel sync block shown in Figure 43. The channel dividers receive a sync signal from the channel sync block only if the APLL is calibrated and locked, unless the APLL locked controlled sync disable bit (Register 0x0405, Bit 3) is set. A channel can be programmed to ignore the sync function by setting the mask Channel 1 sync and mask Channel 0 sync bits (Bits[5:4]) in Register 0x0500. When programmed to ignore the sync, the channel ignores both the user initiated sync signal and the zero delay initiated sync signals, and the channel divider starts toggling, provided that the APLL is calibrated and locked, or if the APLL locked controlled sync disable bit (Register 0x0405, Bit 3) is set. If the output sync function is to be controlled using an M pin, take the following steps: 1. Enable the M pins by writing Register 0x0200 = 0x01. 2. Issue an I/O update (Register 0x0005 = 0x01). 3. Set the appropriate M pin function. If this process is not followed, a sync pulse is issued automatically. |
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