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AD9557 Datasheet(PDF) 18 Page - Analog Devices |
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AD9557 Datasheet(HTML) 18 Page - Analog Devices |
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18 / 95 page  AD9557 Data Sheet Rev. C | Page 18 of 95 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO GROUND (VSS). 1 IRQ 2 SCLK/SCL 3 SDIO/SDA 4 SDO 5 CS 6 DVDD 7 AVDD 8 XOA 9 XOB 10 AVDD 23 AVDD 24 AVDD 25 RESET 26 PINCONTROL 27 SYNC 28 REFA 29 REFA 30 DVDD3 22 AVDD 21 LF_VCO2 TOP VIEW (Not to Scale) AD9557 Figure 2. Pin Configuration Table 20. Pin Function Descriptions Pin No. Mnemonic Input/ Output Pin Type Description 1 IRQ O 3.3 V CMOS Interrupt Request Line. 2 SCLK/SCL I 3.3 V CMOS Serial Programming Clock (SCLK) in SPI Mode. Data clock for serial programming. Open-Collector Serial Clock Pin (SCL) in I2C Mode. Requires a pull-up resistor, usually 2.2 kΩ; the resistor size depends on the number of I2C devices on the bus. 3 SDIO/SDA I/O 3.3 V CMOS Serial Data Input/Output (SDIO) in SPI Mode. When the device is in 4-wire SPI mode, data is written via this pin. In 3-wire SPI mode, both data reads and writes occur on this pin. There is no internal pull-up/pull-down resistor on this pin. Open-Collector Serial Data Pin (SDA) in I2C Mode. Requires a pull-up resistor, usually 2.2 kΩ; the resistor size depends on the number of I2C devices on the bus. 4 SDO O 3.3 V CMOS Serial Data Output. Use this pin to read data in 4-wire mode. There is no internal pull-up/pull-down resistor on this pin. This pin is high impedance in the default 3-wire mode. 5 CS I 3.3 V CMOS Chip Select (SPI), Active Low. When programming a device, this pin must be held low. In systems where more than one AD9557 is present, this pin enables individual programming of each AD9557. This pin has an internal 10 kΩ pull-up resistor. 6, 34, 35 DVDD I Power 1.8 V Digital Supply. 7 AVDD I Power 1.8 V Analog (SYSCLK) Power Supply. 8 XOA I Differential input System Clock Input. XOA contains internal dc biasing. It is recommended to ac couple XOA with a 0.01 µF capacitor, except when using a crystal. If a crystal is used, connect the crystal across XOA and XOB. Single-ended 1.8 V CMOS is also an option but can introduce a spur if the duty cycle is not 50%. When using XOA as a single-ended input, connect a 0.01 µF capacitor from XOB to ground. 9 XOB I Differential input Complementary System Clock Input. Complementary signal to XOA. XOB contains internal dc biasing. It is recommended to ac couple XOB with a 0.01 µF capacitor, except when using a crystal. If a crystal is used, connect the crystal across XOA and XOB. 10, 22, 23, 24 AVDD I Power 1.8 V Analog Power Supply. 11, 17, 18 AVDD I Power 1.8 V Analog (Output Divider and Drivers) Power Supply. 12 OUT1 O HSTL, LVDS, or 1.8 V CMOS Complementary Output 1. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS. |
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