AD9557 datasheet(19/95 Pages) AD

19 / 95 page

Data Sheet

AD9557

Rev. C | Page 19 of 95

Pin No.

Mnemonic

Input/

Output

Pin Type

Description

OUT1

HSTL, LVDS, or

1.8 V CMOS

Output 1. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.

LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent

termination as described in the Input/Output Termination Recommendations

section.

14, 19

AVDD3

Power

3.3 V Analog Power Supply.

OUT0

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

Complementary Output 0. This output can be configured as HSTL, LVDS, or

single-ended 1.8 V or 3.3 V CMOS.

OUT0

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

Output 0. This output can be configured as HSTL, LVDS, or single-ended 1.8 V

or 3.3 V CMOS. LVPECL levels can be achieved by ac coupling and using the

Thevenin-equivalent termination as described in the Input/Output Termination

Recommendations section.

LDO_VCO2

LDO bypass

Output PLL Loop Filter Voltage Regulator. Connect a 0.47 µF capacitor from this

pin to ground. This pin is also the ac ground reference for the integrated output

PLL external loop filter.

LF_VCO2

I/O

Loop filter

Loop Filter Node for the Output PLL. Connect an external 6.8 nF capacitor from

this pin to Pin 20 (LDO_VCO2).

RESET

3.3 V CMOS

Chip Reset. When this active low pin is asserted, the chip goes into reset.

This pin has an internal 50 kΩ pull-up resistor.

PINCONTROL

3.3 V CMOS

Pin Program Mode Enable Pin. When pulled high during startup, this pin enables

pin programming of the AD9557 configuration during startup. If this pin is low

during startup, the user must program the device via the serial port or use values

that are stored in the EEPROM.

SYNC

3.3 V CMOS

Clock Distribution Synchronization Pin. When this pin is activated, output drivers

are held static and then synchronized on a low-to-high transition of this pin. This

pin has an internal 60 kΩ pull-up resistor.

REFA

Differential

input

Reference A Input. This internally biased input is typically ac-coupled and, when

configured as such, can accept any differential signal with single-ended swing up

to 3.3 V. If dc-coupled, this input can be LVPECL, LVDS, or single-ended CMOS.

REFA

Differential

input

Complementary Reference A Input. This pin is the complementary input to Pin

28.

30, 31, 40

DVDD3

Power

3.3 V Digital Power Supply.

REFB

Differential

input

Reference B Input. This internally biased input is typically ac-coupled and, when

configured as such, can accept any differential signal with single-ended swing up

to 3.3 V. If dc-coupled, this input can be LVPECL, LVDS, or single-ended CMOS.

REFB

Differential

input

Complementary Reference B Input. This pin is the complementary input to Pin 32.

36, 37, 38,

M0, M1, M2,

I/O

3.3 V CMOS

(3-level logic

at startup)

Configurable I/O Pins. These pins are 3-level logic at startup and are used for pin

strapping the input and output frequency configuration at startup. Setting

pins to be used for status and control of the AD9557. These pins have both a 30

kΩ pull-up resistor and a 30 kΩ pull-down resistor.

Exposed pad

The exposed pad must be connected to ground (VSS).

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