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AD5933

Data Sheet

Rev. F | Page 6 of 40

I2C SERIAL INTERFACE TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.1

Table 2.

Parameter2

Limit at TMIN, TMAX

Unit

Description

fSCL

400

kHz max

SCL clock frequency

2.5

µs min

SCL cycle time

0.6

µs min

tHIGH, SCL high time

1.3

µs min

tLOW, SCL low time

0.6

µs min

tHD, STA, start/repeated start condition hold time

100

ns min

tSU, DAT, data setup time

t63

0.9

µs max

tHD, DAT, data hold time

µs min

tHD, DAT, data hold time

0.6

µs min

tSU, STA, setup time for repeated start

0.6

µs min

tSU, STO, stop condition setup time

1.3

µs min

tBUF, bus free time between a stop and a start condition

t10

300

ns max

tF, rise time of SDA when transmitting

ns min

tR, rise time of SCL and SDA when receiving (CMOS compatible)

t11

300

ns max

tF, fall time of SCL and SDA when transmitting

ns min

tF, fall time of SDA when receiving (CMOS compatible)

250

ns max

tF, fall time of SDA when receiving

20 + 0.1 Cb4

ns min

tF, fall time of SCL and SDA when transmitting

400

pF max

Capacitive load for each bus line

See Figure 2.

Guaranteed by design and characterization, not production tested.

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH MIN of the SCL signal) to bridge the undefined falling edge of SCL.

Cb is the total capacitance of one bus line in picofarads. Note that tR and tF are measured between 0.3 VDD and 0.7 VDD.

SCL

SDA

t10

t11

START

CONDITION

REPEATED

START

CONDITION

STOP

CONDITION

Figure 2. I2C Interface Timing Diagram

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