AD9910 datasheet(17/64 Pages) AD

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Data Sheet

AD9910

Rev. E | Page 17 of 64

RAM MODULATION MODE

The RAM modulation mode (see Figure 23) is activated via the

RAM enable bit and assertion of the I/O_UPDATE pin (or a

profile change). In this mode, the modulated DDS signal control

parameters are supplied directly from RAM.

The RAM consists of 32-bit words and is 1024 words deep.

Coupled with a sophisticated internal state machine, the RAM

provides a very flexible method for generating arbitrary, time

dependent waveforms. A programmable timer controls the rate

at which words are extracted from the RAM for delivery to the

DDS. Thus, the programmable timer establishes a sample rate at

which 32-bit samples are supplied to the DDS.

The selection of the specific DDS signal control parameters that

serve as the destination for the RAM samples is also programmable

through eight independent RAM profile registers. Select a par-

ticular profile using the three external profile pins (PROFILE[2:0]).

A change in the state of the profile pins with the next rising

edge on SYNC_CLK activates the selected RAM profile.

In RAM modulation mode, the ability to generate a time depen-

dent amplitude, phase, or frequency signal enables modulation

of any one of the parameters controlling the DDS carrier signal.

Furthermore, a polar modulation format is available that partitions

each RAM sample into a magnitude and phase component; 16 bits

are allocated to phase and 14 bits are allocated to magnitude.

PARALLEL

INPUT

PDCLK

SCLK

SDIO

I/O_RESET

PROFILE[2:0]

I/O_UPDATE

RAM

DAC_RSET

IOUT

TxENABLE

DAC FSC

OSK

INVERSE

SINC

FILTER

CLOCK

AMPLITUDE (A)

FREQUENCY

(ω)

PHASE (θ)

DIGITAL

RAMP

GENERATOR

DAC FSC

MULTICHIP

SYNCHRONIZATION

SYSCLK

PLL

÷2

REF_CLK

REFCLK_OUT

XTAL_SEL

PARALLEL DATA

TIMING AND

CONTROL

AD9910

PROGRAMMING

REGISTERS

OUTPUT

SHIFT

KEYING

DATA

ROUTE

AND

PARTITION

CONTROL

INTERNAL CLOCK TIMING

AND CONTROL

Acos (ωt + θ)

Asin (ωt + θ)

DDS

AUX

DAC

8-BIT

DAC

14-BIT

RAM_SWP_OVR

DRCTL

DRHOLD

DROVER

POWER-

DOWN

CONTROL

Figure 23. RAM Modulation Mode

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