OPA189IDGKT datasheet(33/44 Pages) TI1

33 / 44 page

Use a low-

ESR,ceramic bypass

capacitor

Place components

close to device and to

each other to reduce

parasitic errors

Use ground pours for

shielding the input

signal pairs

±IN

V+

+IN

OUT

V±

GND

-V

Place bypass

capacitors as close to

device as possible

(avoid use of vias)

IN±

IN+

OUT

±IN

V+

+IN

OUT

V±

-V

OUT

IN±

IN+

OPA189, OPA2189

www.ti.com

SBOS830C – SEPTEMBER 2017 – REVISED OCTOBER 2018

Product Folder Links: OPA189 OPA2189

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11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp

itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the

analog circuitry.

–

Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground

planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically

separate digital and analog grounds paying attention to the flow of the ground current. For more detailed

information, seeThe PCB is a component of op amp design.

•

To reduce parasitic coupling, run the input traces as far away as possible from the supply or output

traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better

as opposed to in parallel with the noisy trace.

•

Place the external components as close as possible to the device. As illustrated in Figure 52, keeping RF

and RG close to the inverting input minimizes parasitic capacitance.

•

Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

•

Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly

reduce leakage currents from nearby traces that are at different potentials.

•

For best performance, TI recommends cleaning the PCB following board assembly.

•

Any precision integrated circuit may experience performance shifts due to moisture ingress into the

plastic package. Following any aqueous PCB cleaning process, TI recommends baking the PCB

assembly to remove moisture introduced into the device packaging during the cleaning process. A low

temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

11.2 Layout Example

Figure 52. Operational Amplifier Board Layout for Difference Amplifier Configuration

OPA189IDGKT Datasheet(PDF) 33 Page - Texas Instruments

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