ML9060

¡ Semiconductor

9/17

In the Slave mode (M/S pin = “L”):

Leave open the pins OSCR and OSC2 and connect the pin OSC1 to the COM OUT pin of the

ML9060 which has been set in the master mode. The common signal that is input to the pin OSC1

will be used as the internal common signal and is also output via a buffer from the COM OUT

pin.

• COM OUT

This is the common signal output pin. Connect this pin to the OSC1 pin of the ML9060 that is

set in the slave mode.

During operation in the master mode (M/S pin = “H”) for static display, a common signal with

1/128th the frequency of the oscillator is output.

During operation in the master mode (M/S pin = “H”) for 1/2 duty dynamic display, a common

signal with 1/64th the frequency of the oscillator is output.

During operation in the slave mode (M/S pin = “L”), the common signal that is input at the pin

OSC1 is output from this pin via a buffer.

• SYNC

This is the I/O pin for common signal synchronization.

This pin becomes the synchronization signal output pin during operation in the master mode

(M/S pin = “H”) for 1/2 duty dynamic display.

This pin becomes the synchronization signal input pin during operation in the slave mode (M/

S pin = “H”) for 1/2 duty dynamic display.

For cascade operation in the 1/2 duty display mode, connect the SYNC pins of all ML9060 ICs

used together.

During operation in the static display mode, this pin is tied to the “L” level inside the IC.

Connect this pin either to GND or leave it open.

• DATA IN

This is the display data input pin. Input the display data in the sequence of SEG160, SEG159,

... , SEG2, SEG1. The segment is turned ON when the display data is “H” and OFF when “L”.

• DATA OUT

This is the display data output pin. During the static display mode of operation, the data of the

160th stage of the shift register is output from this pin. During the 1/2 duty dynamic display

mode, the data of the 320th stage of the shift register is output from this pin.

• CLOCK IN

This is the input pin for the shift clock of the display data. The display data that is input at the

DATA IN pin is input serially to the shift register at the rising edge of the CLOCK IN signal.

Also, the display data in the shift register is output from the DATA OUT pin at the falling edge

of the CLOCK IN signal.

• CLOCK OUT

This is the output pin for the shift clock of the display data. The shift clock signal that is input

to the CLOCK IN pin is output via a buffer from this pin.

• LOAD IN

This is the input pin for the display data load signal.

The display data in the shift register is output as such to the segment driver when this signal is

at the “H” level. When this signal is made “L”, the shift register is isolated from the segment

drivers, and the display data of the shift register just before this pin goes “L” is retained in the

data latches and transfered to the segment drivers.