AD9116 datasheet(40/52 Pages) AD

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AD9114/AD9115/AD9116/AD9117

Data Sheet

Rev. D | Page 40 of 52

DIGITAL INTERFACE OPERATION

Digital data for the I and Q DACs is supplied over a single

parallel bus (DB[n:0], where n is 7 for the AD9114, is 9 for the

AD9115, is 11 for the AD9116, and 13 for the AD9117)

accompanied by a qualifying clock (DCLKIO). The I and Q

data are provided to the chip in an interleaved double data rate

(DDR) format. The maximum guaranteed data rate is 250 MSPS

with a 125 MHz clock. The order of data pairing and the sampling

edge selection is user programmable using the IFIRST and

IRISING data control bits, resulting in four possible timing

diagrams. These timing diagrams are shown in Figure 89,

Figure 90, Figure 91, and Figure 92.

DCLKIO

NOTES:

1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE

AD9116, AND 13 FOR THE AD9117.

DB[n:0]

I DATA

Q DATA

Figure 89. Timing Diagram with IFIRST = 0, IRISING = 0

DCLKIO

I DATA

Q DATA

NOTES:

1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE

AD9116, AND 13 FOR THE AD9117.

DB[n:0]

Figure 90. Timing Diagram with IFIRST = 0, IRISING = 1

DCLKIO

I DATA

Q DATA

NOTES:

1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE

AD9116, AND 13 FOR THE AD9117.

DB[n:0]

Figure 91. Timing Diagram with IFIRST = 1, IRISING = 0

DCLKIO

I DATA

Q DATA

NOTES:

1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE

AD9116, AND 13 FOR THE AD9117.

DB[n:0]

Figure 92. Timing Diagram with IFIRST = 1, IRISING = 1

Ideally, the rising and falling edges of the clock fall in the center

of the keep-in window formed by the setup and hold times, tS

and tH. Refer to Table 2 for setup and hold times. A detailed

timing diagram is shown in Figure 93.

DCLKIO

DB[n:0]

tS tH

NOTES:

1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE

AD9115, 11 FOR THE AD9116, AND 13 FOR THE AD9117.

Figure 93. Setup and Hold Times for All Input Modes

In addition to the different timing modes listed in Table 2, the

input data can also be presented to the device in either unsigned

binary or twos complement format. The format type is chosen

via the TWOS data control bit.

AD9116 Datasheet(PDF) 40 Page - Analog Devices

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