AD9116 datasheet(7/52 Pages) AD

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Data Sheet

AD9114/AD9115/AD9116/AD9117

Rev. D | Page 7 of 52

DIGITAL SPECIFICATIONS

TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 20 mA, maximum sample rate, unless otherwise noted.

Table 2.

Parameter

Min

Typ

Max

Unit

DAC CLOCK INPUT (CLKIN)

VIH

2.1

VIL

0.9

Maximum Clock Rate

125

MSPS

SERIAL PERIPHERAL INTERFACE

Maximum Clock Rate (SCLK)

MHz

Minimum Pulse Width High

Minimum Pulse Width Low

Minimum SDIO and to SCLK Setup, tDS

Minimum SCLK to SDIO Hold, tDH

Maximum SCLK to Valid SDIO, tDV

Minimum SCLK to Invalid SDIO, tDNV

INPUT DATA

1.8 V Q Channel or DCLKIO Falling Edge

Setup

0.25

Hold

1.2

1.8 V I Channel or DCLKIO Rising Edge

Setup

0.13

Hold

1.1

3.3 V Q Channel or DCLKIO Falling Edge

Setup

−0.2

Hold

1.5

3.3 V I Channel or DCLKIO Rising Edge

Setup

−0.2

Hold

1.6

DVDDIO = 3.3 V

VIH

2.1

VIL

0.9

DVDDIO = 1.8 V

VIH

1.2

1.8

VIL

0.5

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