AD9173 datasheet(32/142 Pages) AD

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AD9173

Data Sheet

Rev. 0 | Page 32 of 142

Table 20. Data Structure per Lane for F = 4 JESD204B Operating Modes1

JESD204B Mode and

Parameters

Link Logical

Lane

Frame 0

Frame 1

Octet 0

Octet 1

Octet 2

Octet 3

Octet 0

Octet 1

Octet 2

Octet 3

Mode 0 (L = 1, M = 2, S = 1,

NP = 16, N = 16)

Lane 0

M0S0[15:8]

M0S0[7:0]

M1S0[15:8]

M1S0[7:0]

M0S1[15:8]

M0S1[7:0]

M1S1[15:8]

M1S1[7:0]

Mode 1 (L = 2, M = 4, S = 1,

NP = 16, N = 16)

Lane 0

M0S0[15:8]

M0S0[7:0]

M1S0[15:8]

M1S0[7:0]

M0S1[15:8]

M0S1[7:0]

M1S1[15:8]

M1S1[7:0]

Lane 1

M2S0[15:8]

M2S0[7:0]

M3S0[15:8]

M3S0[7:0]

M2S1[15:8]

M2S1[7:0]

M3S1[15:8]

M3S1[7:0]

Mode 2 (L = 3, M = 6, S = 1,

NP = 16, N = 16)

Lane 0

M0S0[15:8]

M0S0[7:0]

M1S0[15:8]

M1S0[7:0]

M0S1[15:8]

M0S1[7:0]

M1S1[15:8]

M1S1[7:0]

Lane 1

M2S0[15:8]

M2S0[7:0]

M3S0[15:8]

M3S0[7:0]

M2S1[15:8]

M2S1[7:0]

M3S1[15:8]

M3S1[7:0]

Lane 2

M4S0[15:8]

M4S0[7:0]

M5S0[15:8]

M5S0[7:0]

M4S1[15:8]

M4S1[7:0]

M5S1[15:8]

M5S1[7:0]

1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0.

Table 21. Data Structure per Lane for F = 8 JESD204B Operating Modes1

JESD204B Mode and

Parameters

Link Logical

Lane

Frame 0

Octet 0

Octet 1

Octet 2

Octet 3

Octet 4

Octet 5

Octet 6

Octet 7

Mode 7 (L = 1, M = 4, S = 1,

NP = 16, N = 16)

Lane 0

M0S0[15:8]

M0S0[7:0]

M1S0[15:8]

M1S0[7:0]

M2S0[15:8]

M2S0[7:0]

M3S0[15:8]

M3S0[7:0]

1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0.

PHYSICAL LAYER

The physical layer of the JESD204B interface, hereafter referred

to as the deserializer, has eight identical channels. Each channel

consists of the termination, an equalizer, a clock and data recovery

(CDR) circuit, and the 1:40 demux function (see Figure 50).

EQUALIZER

CDR

1:40

DESERIALIZER

FROM SERDES PLL

SPI

CONTROL

TERMINATION

SERDINx±

Figure 50. Deserializer Block Diagram

JESD204B data is input to the AD9173 via the SERDINx±

differential input pins, per the JESD204B specification.

Interface Power-Up and Input Termination

Before using the JESD204B interface, it must be powered up by

setting Register 0x200, Bit 0 = 0. In addition, each physical lane

(PHY) that is not being used (SERDINx±) must be powered

down. To do so, set the corresponding Bit x for Physical Lane x

in Register 0x201 to 0 if the physical lane is being used, and to 1

if it is not being used.

The AD9173 autocalibrates the input termination to 50 Ω. This

calibration routine is performed automatically when the

JESD204B interface blocks are configured and does not require

any additional SPI register writes.

Receiver Eye Mask

The AD9173 is compatible with the JESD204B specification

regarding the receiver eye mask and is capable of capturing data

that complies with the mask in Figure 51. Figure 51 shows the

receiver eye normalized to the data rate interval. The AD9173

also supports an increased insertion loss limit, as defined in the

Equalization section.

525

–55

–525

1.00

0.35

0.5

0.65

TIME (UI)

RECEIVER EYE MASK

Figure 51. Receiver Eye Mask

Clock Relationships

The following clocks rates are used throughout the rest of the

JESD204B section. The relationship between any of the clocks

can be derived from the following equations:

Data Rate = DAC Rate/Total Interpolation

Lane Rate = (M/L) × NP × (10/8) × Data Rate

Byte Rate = Lane Rate/10

This relationship comes from 8-bit/10-bit encoding, where each

byte is represented by 10 bits.

PCLK Rate = Byte Rate/4

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