AD9173 datasheet(62/142 Pages) AD

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AD9173

Data Sheet

Rev. 0 | Page 62 of 142

SYNCOUT±, SYSREF±, and CLK± Signals

The SYSREF± signal on the AD9173 is a low speed, LVDS,

differential signal. The SYNCOUTx± signals are LVDS or

CMOS selectable. When LVDS mode is selected, use controlled

impedance traces routed as 100 Ω differential impedance and

50 Ω to ground when routing these signals. As with the

SERDIN0± to SERDIN7± data pairs, it is important to keep

these signals separated from potential noise sources, such as

high speed digital signals and noisy supplies. Separate the

SYNCOUTx± signal from other noisy signals because noise on

the SYNCOUTx± may be interpreted as a request for /K/

characters. It is important to keep similar trace lengths for the

CLK± and SYSREF± signals from the clock source to each of

the devices on either end of the JESD204B links (see Figure 86).

If using a clock chip that can tightly control the phase of CLK±

and SYSREF±, the trace length matching requirements are

greatly reduced. The AD9516-0, ADCLK925, and HMC7044

are a few examples of possible clocking solutions depending on

system requirements.

CLOCK SOURCE

(AD9516-1, ADCLK925,

HMC7044)

LANE 0

LANE 1

LANE N – 1

LANE N

DEVICE CLOCK

SYSREF±

SYSREF± TRACE LENGTH

DEVICE CLOCK TRACE LENGTH

DEVICE

Figure 86. SYSREF± Signal and Device Clock Trace Length

AD9173 Datasheet(PDF) 62 Page - Analog Devices