AD9173 datasheet(40/142 Pages) AD

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AD9173

Data Sheet

Rev. 0 | Page 40 of 142

FRAME CLOCK

LMFC

PCLK

DATA

DATA AT Tx FRAMER

ILAS

LMFCRX

TOTAL FIXED LATENCY = 30 PCLK CYCLES

LMFC DELAY = 26 FRAME CLOCK CYCLES

PCB FIXED

DELAY

DATA

ALIGNED LANE DATA

AT Rx DEFRAMER OUTPUT

ILAS

TOTAL VARIABLE

LATENCY = 4

PCLK CYCLES

Tx VAR

DELAY

Rx VAR

DELAY

Figure 63. LMFC Delay Calculation Example

Link Delay Setup Example, with Known Delays

All the known system delays can be used to calculate LMFCVar

and LMFCDel.

The example shown in Figure 63 is demonstrated in the following

steps. Note that this example is in Subclass 1 to achieve determinis-

tic latency, and the example uses the case for F = 2; therefore, the

number of PCLK cycles per multiframe = 16. Because PCBFixed

<< PCLK Period, PCBFixed is negligible in this example and

not included in the calculations.

Find the receiver delays using Table 6.

RxFixed = 13 PCLK cycles

RxVar = 2 PCLK cycles

Find the transmitter delays. The equivalent table in the

example JESD204B core (implemented on a GTH or GTX

gigabit transceiver on a Virtex-6 field programmable gate

array (FPGA)) states that the delay is 56 ± 2 byte clock

cycles.

Because the PCLK rate = ByteRate/4 as described in the

Clock Relationships section, the transmitter delays in

PCLK cycles are calculated as follows:

TxFixed = 54/4 = 13.5 PCLK cycles

TxVar = 4/4 = 1 PCLK cycle

Calculate MinDelayLane as follows:

MinDelayLane = floor(RxFixed + TxFixed + PCBFixed)

= floor(13 + 13.5 + 0)

= floor(26.5)

MinDelayLane = 26

Calculate MaxDelayLane as follows:

MaxDelayLane = ceiling(RxFixed + RxVar + TxFixed +

TxVar + PCBFixed))

= ceiling(13 + 2 + 13.5 + 1 + 0)

= ceiling(29.5)

MaxDelayLane = 30

Calculate LMFCVar as follows:

LMFCVar = (MaxDelay + 1) − (MinDelay − 1)

= (30 + 1) − (26 − 1) = 31 − 25

LMFCVar = 6 PCLK cycles

Calculate LMFCDel as follows:

LMFCDel = (MinDelay − 1) % (PCLKsperMF)

= ((26 − 1)) % 16

= 25 % 16

LMFCDel = 9 PCLK cycles

Write LMFCDel to Register 0x304 for all devices in the

system. Write LMFCVar to Register 0x306 for all devices in

the system.

Link Delay Setup Example, Without Known Delay

If the system delays are not known, the AD9173 can read back

the link latency between LMFCRX for each link (with the

LMFCDel setting subtracted out) and the SYSREF± aligned

LMFC. This information is then used to calculate LMFCVar

and LMFCDel.

Figure 65 shows how DYN_LINK_LATENCY_0 (Register 0x302)

provides a readback showing the delay (in PCLK cycles) between

LMFCRX minus the LMFC_DELAY_x (fixed delay) setting set in

the SPI at that time and the transition from the ILAS to the first

data sample. By repeatedly power cycling and taking this measure-

ment, the minimum and maximum delays across power cycles

can be determined and used to calculate LMFCVar and

LMFCDel.

In Figure 65, for Link A, Link B, and Link C, the system

containing the AD9173 (including the transmitter) is power

cycled and configured 20 times. The AD9173 is configured as

described in the Sync Procedure section. Because the purpose

of this exercise is to determine LMFCDel and LMFCVar, the

LMFCDel value is programmed to 0 and the DYN_LINK_

LATENCY_0 value is read from Register 0x302. The variation

in the link latency over the 20 runs is shown in Figure 65,

described as follows:

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