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Data Sheet

AD9173

Rev. 0 | Page 29 of 142

JESD204B SERIAL DATA INTERFACE

JESD204B OVERVIEW

The AD9173 has eight JESD204B data ports that receive data.

The eight JESD204B ports can be configured as part of a single

or dual JESD204B link that uses a single system reference

(SYSREF±) and device clock (CLKIN±).

The JESD204B serial interface hardware consists of three layers:

the physical layer, the data link layer, and the transport layer.

These sections of the hardware are described in subsequent

sections, including information for configuring every aspect of

the interface. Figure 49 shows the communication layers

implemented in the AD9173 serial data interface to recover the

clock and deserialize, descramble, and deframe the data before it

is sent to each of the digital signal processing channelizers of

the device.

The physical layer establishes a reliable channel between the

transmitter (Tx) and the receiver (Rx), and the data link layer is

responsible for unpacking the data into octets and descrambling

the data. The transport layer receives the descrambled

JESD204B frames and converts them to DAC samples.

A number of JESD204B parameters (L, F, K, M, N, NP, S, HD)

define how the data is packed and tell the device how to turn

the serial data into samples. These parameters are defined in

detail in the Transport Layer section. The AD9173 also has a

descrambling option (see the Descrambler section for more

information). The AD9173 has the ability to use 12-bit packing

mode (NP = 12, N = 11 or 12) to increase the maximum data

rate achievable by this device for applications that do not

require 16-bit resolution capabilities.

The AD9173 has multiple single-link and dual-link mode

options available for various application purposes. These modes

and their respective JESD204B link parameters are described in

Table 15 and Table 16.

There are different interpolation combinations available for the

channel and main datapaths, as well as whether single-link and

dual-link options are available depending on which JESD204B

mode is chosen. Table 13 lists the possible link and

interpolation combinations available.

The AD9173 has two DAC outputs; however, for the purposes

of complex signal processing on chip, the converter count,

represented by the M JESD204B parameter, reflects the number

of complex subchannels of data required per link when using a

total interpolation greater than 1×. The number of complex

subchannels of data per link required to be sent to the device

also depends on the number of channelizers being used, based

on the mode of operation chosen. If the channelizer datapaths

are bypassed (channel interpolation is set to 1×) and the main

datapath interpolation is set to 1×, the converter count (M)

reflects the number of real converters per link being used in the

mode of operation; in this case, complex data is not required.

For a particular JESD204B mode of operation, the following

relationships exist:

Total Interpolation = Channel Interpolation ×

Main Interpolation

Data Rate = DAC Rate/Total Interpolation

Lane Rate = (M/L) × NP × (10/8) × Data Rate

where:

Lane Rate must be between 3 Gbps and 15 Gbps.

M, L, and NP are JESD204B link parameters for the chosen

JESD204B operating mode.

Achieving and recovering synchronization of the lanes is

important. To simplify the interface to the transmitter, the

AD9173 designates a master synchronization signal for each

JESD204B link. The SYNCOUT0± and SYNCOUT1± pins are

used as the master signal for all lanes on each link. If any lane in a

link loses synchronization, a resynchronization request is sent

to the transmitter via the synchronization signal of the link. The

transmitter stops sending data and instead sends synchronization

characters to all lanes in that link until resynchronization is

achieved.

DESERIALIZER

DATA LINK

LAYER

TRANSPORT

LAYER

SERDIN0±

SYSREF±

SERDIN7±

I DATA[15:0]

Q DATA[15:0]

COMPLEX DATA

PER CHANNELIZER

SYNCOUT1±

SYNCOUT0±

PHYSICAL

LAYER

DESERIALIZER

FRAME TO

SAMPLES

QBD/

DESCRAMBLER

Figure 49. Functional Block Diagram of Serial Link Receiver

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