LDS8161/41

© 2009 IXYS Corp.

4

Doc. No. 8141/61_DS, Rev. N1.0

Characteristics subject to change without notice

I

Over recommended operating conditions unless otherwise specified for 2.7

VIN 5.5V, over full ambient temperature range -40 to +85ºC.

Symbol

Parameter

Min

Max

Unit

SCL Clock Frequency

0

400

kHz

Hold Time (repeated) START condition

0.6

µs

LOW period of the SCL clock

1.3

µs

HIGH period of the SCL clock

0.6

µs

Set-up Time for a repeated START condition

0.6

µs

Data In Hold Time

0

0.9

ns

Data In Set-up Time

100

ns

Rise Time of both SDAT and SCLK signals

300

ns

Fall Time of both SDAT and SCLK signals

300

ns

Set-up Time for STOP condition

0.6

µs

Bus Free Time between a STOP and START condition

1.3

µs

SCLK Low to SDAT Data Out and ACK Out

0.9

µs

Data Out Hold Time

300

ns

Figure 1: I

READ OPERATION:

Option 1: Standard protocol sequential read:

S

Slave Address

R

A

Data 0

A

Data 1

A

Data 2

Data n

A*

P

From: Reg. m

Reg. m+1

Reg. m+2

Reg. m+n,

where Reg. m is the last addressed in the write operation register

Option 2: Random access:

S

Slave Address

R

A

Data m

A*

P

From reg. m, where Reg. m is the last addressed in the write operation register

Option 3: Random access with combined (extended) protocol:

S

Slave Address

W

A

Register Address m

A

Sr

Slave Address

R

A

Data m

A*

P

WRITE OPERATION:

Option 1: Standard protocol sequencial write:

S

Slave Address

W

A

Register Address m

A

Data 0

A

Data 1

A

Data 2

Data k

A*

P

To: Reg. m

Reg. m+1

Reg. m+2

Reg. m+k