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LDS8161 Datasheet(PDF) 5 Page - IXYS Corporation |
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LDS8161 Datasheet(HTML) 5 Page - IXYS Corporation |
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5 / 22 page ![]() LDS8161/41 © 2009 IXYS Corp. 5 Doc. No. 8141/61_DS, Rev. N1.0 Characteristics subject to change without notice Option 2: Combined (extended) protocol: S Slave Address W A Register Address m A Sr Slave Address W A Data A* P To: Reg. m S: Start Condition Sr Start Repeat Condition R, W: Read bit (1), Write bit (0) A: Acknowledge (SDAT high) A*: Not Acknowledge (SDAT low) P: Stop Condition Slave Address: Device address 7 bits (MSB first). Register Address: Device register address 8 bits Data: Data to read or write 8 bits - send by master - send by slave I 2C BUS PROTOCOL Standard protocol Combined protocol: WRITE INSTRUCTION SEQUENCE Standard protocol: Write Instruction Example - Setting 20mA Current in LEDB1 and LEDB2 |
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