AD5689 datasheet(5/24 Pages) AD

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Data Sheet

AD5689/AD5687

Rev. B | Page 5 of 24

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.

VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.

Table 4.

1.62 V ≤ VLOGIC < 2.7 V

2.7 V ≤ VLOGIC ≤ 5.5 V

Parameter1

Symbol

Min

Max

Min

Max

Unit

SCLK Cycle Time

SCLK High Time

SCLK Low Time

SYNCE to SCLK Falling Edge Setup Time

Data Setup Time

Data Hold Time

SCLK Falling Edge to SYNCE Rising Edge

Minimum SYNCE High Time

SYNCE Rising Edge to SYNCE Rising Edge (DAC Register Updates)

870

830

SYNCE Falling Edge to SCLK Fall Ignore

t10

LDACE Pulse Width Low

t11

SYNCE Rising Edge to LDACE Rising Edge

t12

SYNCE Rising Edge to LDACE Falling Edge

t13

LDACE Falling Edge to SYNCE Rising Edge

t14

840

800

Minimum Pulse Width Low

t15

Pulse Activation Time

t16

Power-Up Time2

4.5

μs

1Guaranteed by design and characterization; not production tested.

2 Time to exit power-down to normal mode of operation, SYNCE rising edge to 90% of DAC midscale value, with output unloaded.

SCLK

SYNC

SDIN

t14

DB23

t10

t11

t12

t13

t15

t16

VOUT

DB0

Figure 2. Serial Write Operation

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