Data Sheet

AD5689/AD5687

Rev. B | Page 9 of 24

2B

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

12

11

10

1

3

4

SDIN

SYNC

SCLK

9

2

GND

NC

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO

THIS PIN.

2. THE EXPOSED PAD MUST BE TIED TO GND.

TOP VIEW

(Not to Scale)

AD5689/

AD5687

Figure 6. 16-Lead LFCSP Pin Configuration

1

2

3

4

5

6

7

8

NC

GND

NC

SDO

16

15

14

13

12

11

10

9

RESET

SDIN

SYNC

GAIN

LDAC

SCLK

RSTSEL

NOTES

1. NC = NO CONNECT. DO NOT CONNECT

TO THIS PIN.

TOP VIEW

(Not to Scale)

AD5689/

AD5687

Figure 7. 16-Lead TSSOP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

LFCSP

TSSOP

1

3

Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

2

4

GND

Ground Reference Point for All Circuitry on the AD5689/AD5687.

3

5

Power Supply Input. The AD5689/AD5687 can be operated from 2.7 V to 5.5 V. Decouple the supply

with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

4

2

NC

No Connect. Do not connect to this pin.

5

7

Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

6

8

SDO

Serial Data Output. SDO can be used to daisy-chain a number of AD5689/AD5687 devices together,

or it can be used for readback. The serial data is transferred on the rising edge of SCLK and is valid

on the falling edge of the clock.

7

9

A

A

A

can be operated in two modes: asynchronous and synchronous. Pulsing this pin low allows

either or both DAC registers to be updated if the input registers have new data; both DAC outputs can

be updated simultaneously. This pin can also be tied permanently low.

8

10

GAIN

9

11

Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V.

10

12

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. Data can be transferred at rates of up to 50 MHz.

11

13

A

Active Low Control Input. This is the frame synchronization signal for the input data. When

A

A

goes low, data is transferred in on the falling edges of the next 24 clocks.

12

14

SDIN

Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the

falling edge of the serial clock input.

13

15

A

Asynchronous Reset Input. The

A

A

input is falling edge sensitive. When

A

A

is low, all

A

A

pulses are ignored. When

A

A

is activated, the input register and the DAC register are updated with

zero scale or midscale, depending on the state of the RSTSEL pin. If the pin is forced low at power-up,

the POR circuit does not initialize correctly until the pin is released.

14

16

RSTSEL

Power-On Reset Select. Tying this pin to GND powers up both DACs to zero scale. Tying this pin to

15

1

Reference Input Voltage.

16

6

NC

No Connect. Do not connect to this pin.

17

N/A

EPAD

Exposed Pad. The exposed pad must be tied to GND.