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AD5689/AD5687

Data Sheet

Rev. B | Page 18 of 24

22B

SERIAL INTERFACE

The AD5689/AD5687 have a 3-wire serial interface (

SYNCE

SCLK, and SDIN) that is compatible with SPI, QSPI™, and

MICROWIRE® interface standards as well as most DSPs. See

Figure 2 for a timing diagram of a typical write sequence. The

AD5689/AD5687 contain an SDO pin that allows the user to

daisy-chain multiple devices together (see the Daisy-Chain

Operation section) or read back data.

40B

Input Shift Register

The input shift register of the AD5689/AD5687 is 24 bits wide,

and data is loaded MSB first (DB23). The first four bits are the

command bits, C3 to C0 (see Table 9), followed by the 4-bit DAC

address bits, composed of DAC B, DAC A, and two don’t care

bits set to 0 (see Table 8). Finally, the data-word completes the

input shift register.

The data-word comprises 16-bit or 12-bit input code, followed by

zero don’t care bits for the AD5689 or four don’t care bits for the

AD5687, as shown in Figure 38 and Figure 39, respectively.

These data bits are transferred to the input shift register on the

24 falling edges of SCLK and updated on the rising edge of

SYNCE

Commands can be executed on individual DAC channels or on

both DAC channels, depending on the address bits selected.

Table 8. Address Commands

Address (n)

Selected DAC Channel

DAC B

DAC A

DAC B

DAC A and DAC B

Table 9. Command Definitions

Command

Description

No operation

Write to Input Register n (dependent on

LDACE

)

Update DAC Register n with contents of Input Register n

Write to and update DAC Channel n

Power down/power up DAC

Hardware

LDACE

mask register

Software reset (power-on reset)

Reserved

Set up DCEN register (daisy-chain enable)

Set up readback register (readback enable)

Reserved

…

Reserved

No operation, daisy-chain mode

ADDRESS BITS

COMMAND BITS

DAC

D15 D14 D13 D12 D11 D10

DB23 (MSB)

DB0 (LSB)

DATA BITS

Figure 38. AD5689 Input Shift Register Content

ADDRESS BITS

COMMAND BITS

DAC

D11 D10

DB23 (MSB)

DB0 (LSB)

DATA BITS

Figure 39. AD5687 Input Shift Register Content

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