AD9144 datasheet(32/125 Pages) AD

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AD9144

Data Sheet

Rev. B | Page 32 of 125

For safety, add a guard band of 1 PClock cycle to each end of

the link delay as in the following equations:

LMFCVar = (MaxDelay + 1) − (MinDelay − 1)

Note that if LMFCVar must be more than 10, the AD9144 is

unable to tolerate the variable delay in the system.

For Subclass 1

LMFCDel = ((MinDelay − 1) × PClockFactor) % K

For Subclass 0

LMFCDel = (MinDelay − 1) % PClockPerMF

Program the same LMFCDel and LMFCVar across all links and

devices.

See the Link Delay Setup Example, with Known Delays section

for an example calculation.

Without Known Delays

If comprehensive delay information is not available or known,

the AD9144 can read back the link latency between the LMFCRX

and the last arriving LMFC boundary in PClock cycles. This

information is then used to calculate LMFCVar and LMFCDel.

For each link (on each device)

1. Power up the board.

2. Follow the steps in Table 15 through Table 21 of the Device

Setup Guide.

3. Set the subclass and perform a sync. For one-shot sync,

perform the writes in Table 33. See the Syncing LMFC

Signals section for alternate sync modes.

4. Record DYN_LINK_LATENCY_0 (Register 0x302) as a

value of Delay for that link and power cycle.

5. Record DYN_LINK_LATENCY_1 (Register 0x303) as a

value of Delay for that link and power cycle the system.

Repeat Step 1 to Step 5 twenty times for each device in the

system. Keep a single list of the Delay values across all runs and

devices.

Table 33. Register Configuration and Procedure for One-

Shot Sync

Addr.

Bit.

No.

Value1

Variable

Description

0x301

Subclass

Set subclass

0x03A

0x01

Set sync mode to

one-shot sync

0x03A

0x81

Enable the sync

machine

0x03A

0xC1

Arm the sync

machine

SYSREF±

Signal

If Subclass = 1, ensure

that at least one

SYSREF± edge is sent

to the device.

0x300

Enable the links

CheckSumMode

See the JESD204B

Setup section

DualLink

See the JESD204B

Setup section

CurrentLink

Set to 0 to access

Link 0 status or 1

for Link 1 status

readbacks. See the

JESD204B Setup

section.

[1:0]

EnLinks

EnLinks = 3 if in

DualLink mode to

enable Link 0 and

Link 1; EnLinks = 1 if

not in DualLink mode

to enable Link 0

0x denotes a register value that the user must fill in. See the Variable and

Description columns for information on selecting the appropriate register value.

The list of delay values is used to calculate LMFCDel and

LMFCVar; however, first some of the delay values may need to

be remapped.

The maximum possible value for DYN_LINK_LATENCY_x

is one less than the number of PClocks in a multiframe

(PClocksPerMF). It is possible that a rollover condition may be

encountered, meaning the set of recorded Delay values might roll

over the edge of a multiframe. If so, Delay values may be near

both 0 and PClocksPerMF. If this occurs, add PClocksPerMF to

the set of values near 0.

For example, for Delay value readbacks of 6, 7, 0, and 1, the 0

and 1 Delay values must be remapped to 8 and 9, making the

new set of Delay values 6, 7, 8, and 9.

AD9144 Datasheet(PDF) 32 Page - Analog Devices

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