AD9144 datasheet(29/125 Pages) AD

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Data Sheet

AD9144

Rev. B | Page 29 of 125

DAC PLL SETUP

This section explains how to select the appropriate LODivMode,

RefDivMode, and BCount in the Step 1: Start Up the DAC

section. These parameters depend on the desired DAC clock

frequency (fDACCLK) and DAC reference clock frequency (fREF).

When using the DAC PLL, the reference clock signal is applied

to the CLK± differential pins (Pin 2 and Pin 3).

Table 23. DAC PLL LODivMode Settings

DAC Frequency Range (MHz)

LODivMode,

1500 to 2800

750 to 1500

420 to 750

Table 24. DAC PLL RefDivMode Settings

DAC PLL Reference

Frequency (fREF) (MHz)

Divide by

(RefDivFactor)

RefDivMode,

35 to 80

80 to 160

160 to 320

320 to 640

640 to 1000

The VCO frequency (fVCO) is related to the DAC clock frequency

according to the following equation:

fVCO = fDACCLK × 2LODivMode+ 1

where 6 GHz ≤ fVCO ≤ 12 GHz.

BCount must be between 6 and 127 and is calculated based on

fDACCLK and fREF as follows:

BCount = floor((fDACCLK)/(2 × fREF/RefDivFactor))

where RefDivFactor = 2RefDivMode (see Table 24).

Finally, to finish configuring the DAC PLL, set the VCO control

registers up as described in Table 25 based on the VCO

frequency (fVCO). Write the registers listed in the table with the

corresponding LookUpVals.

Table 25. VCO Control Lookup Table Reference

VCO Frequency

Range (GHz)

0x1B5

Setting

0x1BB

Setting

0x1C5

Setting

fVCO < 6.3

0x08

0x03

0x07

6.3 ≤ fVCO < 7.25

0x09

0x03

0x06

fVCO ≥ 7.25

0x09

0x13

0x06

For more information on the DAC PLL, see the DAC Input

Clock Configurations section.

INTERPOLATION

The transmit path can use zero to three cascaded interpolation

filters, which each provides a 2× increase in output data rate and

a low-pass function. Table 26 shows the different interpolation

modes and the respective usable bandwidth along with the

maximum fDATA rate attainable.

Table 26. Interpolation Modes and Their Usable Bandwidth

Interpolation

Mode

InterpMode

Usable

Bandwidth

Max fDATA (MHz)

1× (bypass)

0x00

0.5 × fDATA

1060 (SERDES

limited)

2×

0x01

0.4 × fDATA

1060 (SERDES

limited)

4×

0x03

0.4 × fDATA

700

8×

0x04

0.4 × fDATA

350

The usable bandwidth is defined for 1×, 2×, 4×, and 8× modes

as the frequency band over which the filters have a pass-band

ripple of less than ±0.001 dB and an image rejection of greater

than 85 dB. For more information, see the Interpolation Filters

section.

JESD204B SETUP

This section explains how to select a JESD204B operating mode

for a desired application. This section defines appropriate values

for CheckSumMode, UnusedLanes, DualLink, CurrentLink,

Scrambling, L, F, K, M, N, NP, Subclass, S, HD, Lane0Checksum,

and Lanes needed for the Step 3: Transport Layer section.

Note that DualLink, Scrambling, L, F, K, M, N, NP, S, HD, and

Subclass must be set the same on the transmit side.

For a summary of how a JESD204B system works and what each

parameter means, see the JESD204B Serial Data Interface section.

Available Operating Modes

Table 27. JESD204B Operating Modes (Single-Link Only)

Mode

Parameter

M (Converter Count)

L (Lane Count)

S ((Samples per Converter) per Frame)

F ((Octets per Frame) per Lane)

Table 28. JESD204B Operating Modes (Single- or Dual-Link)

Mode

Parameter

M (Converter Count)

L (Lane Count)

S ((Samples per Converter) per Frame)

F ((Octets per Frame) per Lane)

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