SCD1284 datasheet(78/176 Pages) INTEL

Part #	SCD1284

Description	IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

PDF	176 Pages

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Manufacturer	INTEL [Intel Corporation]

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CD1284 — IEEE 1284-Compatible Parallel Interface Controller

Datasheet

5.12.3

State Machine

The parallel port is controlled by a large synchronous state machine. The state machine is based on

the IEEE STD 1284 specification and conforms to all the functional modes (except extensibility

link options, none of which are currently — as of the print date of this document — defined).

5.12.4

Configuration

At power-up, the interface begins in Compatibility mode (Centronics mode) ready to accept data

from the master. Only the ETxfr bit (PCR[5]) is required to allow transfers in Compatibility mode

(parallel port only; datapath section is separate). PCR[7:5] enable transfers and Negotiation and

Manual modes.

Outputs

AkDaRq

PError

AkDaRq

nAkRev

USER1

PerBsy

BUSY

PerBsy

PerAck

nWait

PerClk

ACK*

PerClk

Intr

nDatAv

FAULT*

nDatAv

nPerReq

USER2

XFlag

SELECT

XFlag

USER3

Table 20. Signal Names (Sheet 2 of 2)

Names

Compatibility

Rev. NB

Rev. BT

ECP

EPP

Figure 11. FIFO Data Path Functional Diagram — Receive

FIFO (64 BYTES)

TAG (64 BITS)

DB[15:8]

DB[7:0]

PFSR

(RECEIVE)

STATUS

TAG

TAG BIT

STATUS

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