SCD1284 datasheet(33/176 Pages) INTEL

33 / 176 page

IEEE 1284-Compatible Parallel Interface Controller — CD1284

Datasheet

As described above, Channel 0 is a separate entity comprised of its own FIFO and DMA data

interface, as well as a high-speed state machine that handles all of the modes defined in the IEEE

STD 1284 specification. Channel 0 performs the slave, or peripheral, function of the IEEE STD

1284 interface and can be programmed to accept negotiations into any or all of the defined modes.

The MPU aids the parallel port by providing the local access (through the CAR) and provides

interrupt support (generation and response). However, this is the only action where the MPU is

involved in parallel port service-request activities.

5.2

CPU Interface

The CPU interface comprises an 8-bit bidirectional data bus, a 7-bit address bus, a 16-bit DMA

port and control inputs to identify the type of I/O cycle occurring. Although the strobe names and

basic timing match that of the Motorola 68000 family, the CD1284 fits easily into any CPU

environment.

In most cases, when the CPU reads or writes an internal CD1284 location, it actually accesses a

location in a RAM array to serve as a bank of registers. Some locations however, are mapped to

actual hardware resources for example, when a hard output signal is required (such as a service-

request output in the SVRR) or when it is necessary to read the actual state of an input (such as a

modem input).

The CD1284 is a synchronous device. All internal operations occur on edges and levels (phases) of

the internal clock. The internal clock is generated by dividing the external (system) clock by two.

When the CPU performs an I/O cycle with the CD1284, it strobes; address, and data are sampled

on the rising edges of the internal clock. As illustrated in Chapter 8.0, the external control signals

must meet setup times with respect to system clock edges. Once a cycle starts, the sequence of

events is locked to the clock of the CD1284. With events (address setup, write data setup, and read

data available) occurring at predictable times.

It is not necessary to design a synchronous interface to the CD1284. In an asynchronous design, the

DTACK* (Data Transfer Acknowledge) signal indicates that the CD1284 has completed the

requested data transfer for all I/O cycles except DMA. DTACK* can be an input to wait-state

generation logic that pauses the CPU until the operation is complete. If the CS* and DS* strobes

(Chip Select and Data Strobe) do not meet the minimum setup time with respect to the system

clock edge, the CD1284 does not detect the I/O request, and the cycle delays for two full-system

clock cycles, meeting the setup time. The I/O cycle commences and follows the predictable timing

with DTACK* signaling the end.

5.2.1

Read Cycles

Read cycles are initiated when both the CS* and DS* inputs are activated and the R/W* (read/

write) input is high. All strobes and address inputs must meet the setup times as specified in

Chapter 8.0. Both the CS* and DS* signals must be valid for a cycle to start. Cycle times are

measured from whichever of the two signals goes active last. The CD1284 signals the completion

of the read cycle (placing the data from the addressed register on the data bus pins) by activating

DTACK*. The read cycle terminates when the CPU removes CS* and DS*.

SCD1284 Datasheet(PDF) 33 Page - Intel Corporation

SCD1284 Datasheet(HTML) 33 Page - Intel Corporation

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