SCD1284 datasheet(32/176 Pages) INTEL

Part #	SCD1284

Description	IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

PDF	176 Pages

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Manufacturer	INTEL [Intel Corporation]

Direct Link	http://www.intel.com

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CD1284 — IEEE 1284-Compatible Parallel Interface Controller

Datasheet

The serial data channels are made of ‘bit engines’ that off-load the task of receiving and

transmitting each bit from the MPU. When receiving data and after processing a complete bit, the

bit engines interrupt the MPU so that it can perform the next required task. For example, the MPU

takes the bit and adds it to a character being assembled. When transmitting, it sends the bit engine

the next bit of the character being transmitted. The MPU is not concerned with basic bit timing; this

task is handled by the bit engines, leaving the MPU free to perform higher-level processing, such as

detecting special characters.

Figure 3. CD1284 Functional Block Diagram

BUS

INTERFACE

AND DMA

LOGIC

PARALLEL

PORT FIFO

PARALLEL

PORT LOGIC

CONTROL STATE

MACHINE

INTERRUPT

LOGIC

MPU

ROM

RAM

CHANNEL 2

LOGIC AND BIT

TIMING

CHANNEL 3

LOGIC AND BIT

TIMING

Figure 4. Internal Address Generation

CHANNEL 2 REGISTERS

CHANNEL 3 REGISTERS

CPU

ADDRESS

GENERATION

CAR

RAM REGISTER

ARRAY

PARALLEL PORT

REGISTERS

(CHANNEL 0)

SCD1284 Datasheet(PDF) 32 Page - Intel Corporation

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