SCD1284 datasheet(86/176 Pages) INTEL

86 / 176 page

CD1284 — IEEE 1284-Compatible Parallel Interface Controller

Datasheet

5.17

Hardware Configurations

The simplicity of the CPU interface to the CD1284 allows the device to be designed into systems

that employ popular microprocessors such as the Intel 80x86 family (8086, 80286, 80386, and so

on), the Motorola family (68000, 68010, 68020, and so on), the National Semiconductor 32x32

family (32CG16, 32332, 32532, 32GX32, and so on), and the AMD 29000.

5.17.1

Interfacing to an Intel Microprocessor-Based System

With very little extra logic, the CD1284 can interface to any system based on a processor in the

Intel 80x86 family. Figure 15 shows a generalized view of an I/O-mapped interface with an 80286-

based system. To provide the proper strobes and controls, the IOR* and IOW* control strobes

synthesize the DS* and R/W* signals. DTACK* is used as an input to wait-state-generation logic

that holds the processor (if necessary) until the CD1284 has completed the I/O request.

5.17.2

Interfacing to a Motorola Microprocessor-Based System

Interfacing to a 68000 family device is relatively simple. Bus timing and the interface signal

definitions closely match those of the 68000 microprocessor, which allows a direct connection in

most cases. With later versions (68020, 68030), some additional logic is required to generate the

DSACK0* and DSACK1* functions that replace the DTACK* on earlier devices. The example in

Figure 16 on page 88 shows a generalized interface to a 68020 device.

5.17.3

Interfacing to a National Semiconductor

Microprocessor-Based System

The connections between the CD1284 and an NS32000 (32GX320, 32CG16, and so on) embedded

controller are also relatively simple. As with the Intel devices, cycles are controlled by the DS*,

CS*, and R/W* signals synthesized from the available I/O-control signals. I/O-cycle extensions

(wait states) are generated by logic connected to the DTACK* signal. All necessary controls are

available to prevent multiple read/write cycles in the CD1284 FIFOs when using memory-mapped

I/O.

Figure 14. External Buffer Control

DIR

TO CABLE

TO CD1284

PDBEN

EBDIR

Impedance matching and protection circuitry

(see Figure 13) as required for the 74AS245.

SCD1284 Datasheet(PDF) 86 Page - Intel Corporation