SCD1284 datasheet(40/176 Pages) INTEL

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CD1284 — IEEE 1284-Compatible Parallel Interface Controller

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One reason a design might make use of this method is that limited board space is available for the

additional hardware address decoding required to generate the four SVCACK* and DGRANT*

control signals. The advantage is that the system need not constantly poll the CD1284 for active

service requests. It is interrupted when a request is posted, then examines internal CD1284

registers to determine the source and channel number generating the request. For this method, tie

the four SVCACK* and DGRANT* input pins inactive (logic ‘1’). This prevents possible false

activation of a service-acknowledge cycle that occurs due to noise. Terminate these pins with a

resistor (approximately 1 k

Ω) not hardwired to V

CC.

5.3.3

Serial Service Request Polling

In Poll mode, the CPU periodically checks the CD1284 to see if there are any active service

requests. If it detects any, it proceeds to service them by a software-driven technique. There are

several registers within the CD1284 specifically provided to facilitate Poll-mode service-request

detection and acknowledgment. These are the SVRR, RIR, TIR, PIR, MIR, RIVR, TIVR, and

MIVR. Chapter 7.0 provides detailed bit definitions for these registers.

The SVRR is the master service-request register. The least-significant three bits (bits 2:0 — SRM,

SRT, and SRR) reflect the inverse of the state of the three service-request output pins

(SVCREQM*, SVCREQT*, and SVCREQR*). For example, if SRR[0] is ‘1’, it indicates that

there is a pending active serial receive data service request, and that the SVCREQR* output pin is

active (low). The CPU now can determine with a single read if the CD1284 requires any service

and which pins are active.

Each service request type has an interrupt request register: RIR for receive, TIR for transmit, and

MIR for modem. These are the special purpose registers used with the CAR to force the context

switch and start a service-acknowledge procedure. When a service request of a particular type is

pending, the corresponding Interrupt Request register is set by the MPU with the appropriate data

to cause the context switch to the requested type and the requesting channel.

When the CPU is ready to service the request, it reads the contents of the request register and

copies it into the CAR. This write into the CAR forces the context switch and the CD1284 is ready

to be serviced. The result is the same as performing a service-acknowledge cycle with the

SVCACK* pin.

Each of the Interrupt Request registers provide the channel number by requesting service in the

least-significant two bits. The most-significant three bits provide status and control over internal

interrupt sequencing. The middle three bits contain a code used by the MPU at the end of a

hardware service-acknowledge cycle (write to the EOSRR) to indicate the type of acknowledge

cycle that is ending. Each of the three registers has a unique code in these three bits to select the

proper service-acknowledge type, but these are meaningless in Poll-mode operation.

At the end of a service-request operation, the CPU must inform the CD1284 that the request is

satisfied and to take it out of the service-request context. This is done by rewriting the value that

was in the interrupt request register after clearing the upper two bits.

As with the hardware-driven request/acknowledge procedure, the Virtual registers should only be

accessed after the context switch is made. Their contents are undefined until this time.

SCD1284 Datasheet(PDF) 40 Page - Intel Corporation

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