ML9042 datasheet(12/58 Pages) OKI

12 / 58 page

FEDL9042-01

OKI Semiconductor

ML9042-xx

12/58

2) READ MODE (Timing for output to the CPU)

(VDD = 2.7 to 4.5 V, Ta = –40 to +85°C)

Parameter

Symbol

Min.

Typ.

Max.

Unit

RW/SI, RS1, RS0/CSB Setup Time

—

E/SHTB Pulse Width

450

—

RW/SI, RS1, RS0/CSB Hold Time

—

E/SHTB Rise Time

—

125

E/SHTB Fall Time

—

125

E/SHTB Pulse Width

430

—

E/SHTB Cycle Time

1000

—

DB0(SO) to DB7 Output Data Delay Time

—

350

DB0(SO) to DB7 Output Data Hold Time

—

Note: A load capacitance of each of DB0(SO) to DB7 must be 50 pF or less.

(VDD = 4.5 to 5.5 V, Ta = –40 to +85°C)

Parameter

Symbol

Min.

Typ.

Max.

Unit

RW/SI, RS1, RS0/CSB Setup Time

—

E/SHTB Pulse Width

220

—

RW/SI, RS1, RS0/CSB Hold Time

—

E/SHTB Rise Time

—

125

E/SHTB Fall Time

—

125

E/SHTB Pulse Width

220

—

E/SHTB Cycle Time

500

—

DB0(SO) to DB7 Output Data Delay Time

—

250

DB0(SO) to DB7 Output Data Hold Time

—

Note: A load capacitance of each of DB0(SO) to DB7 must be 50 pF or less.

RS1, RS0/CSB

VIH

VIL

VIH

VIL

VIH

VIL

VIH

0.8VDD

0.2VDD

0.8VDD

0.2VDD

RW/SI

E/SHTB

DB0(SO) to DB7

Output

Data

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