CD1283 datasheet(79/94 Pages) INTEL

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IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

Note:

For synchronous systems, it is necessary to determine the clock cycle number so that interface

circuitry can stay in lock-step with the device. CLK numbers can be determined if RESET* is

released within the range ta–tb; ta is defined as 10 ns minimum, after the rising edge of the clock; tb

is defined as 5 ns minimum, before the next rising edge of the clock. If these conditions are met, the

cycle starting after the second rising edge will be C1. See the synchronous timing diagrams for

additional information. Clock numbers are not important in asynchronous systems.

The following timing numbers are for the back-to-back asynchronous DMA timing diagrams.

t25

Hold time, DMAACK* active (DMA read/write)

3 CLK

t26

Delay, data valid after falling edge DMAACK* (DMA read)

0.5 CLK

+ 20

1.5 CLK

+ 25

t27

Hold time, data valid after rising edge DMAACK* (DMA read)

t28

Inactive time, DMAACK* (DMA read/write)

t29

Hold time, DMAREQ* rising edge after

DMAACK* falling edge (DMA read/write)

1 CLK

+ 15

t30

Hold time, DMAACK* active (DMA write)

2.5 CLK

t31

Delay, data valid after falling edge DMAACK* (DMA write)

1.5 CLK

NOTES:

1. Timing numbers for RESET* and CLK are valid for both asynchronous and synchronous specifications. The device will

operate on any clock with a 40–60 or better duty cycle.

2. On host-I/O cycles, immediately following SVCACK* cycles and writes to EOSRR, DTACK* will be delayed by 20 CLKs (1 ms

@ 20 MHz; 800 ns @ 25 MHz). On systems that do not use DTACK* to signal the end of the I/O cycle, wait states or some

other form of delay generation must be used to assure that the CD1283 is not accessed until after this time period.

3. As TCLK increases, device performance decreases. A minimum clock frequency of 25 MHz is required to guarantee specified

performance. The recommended maximum TCLK is 1000 ns.

4. DTACK* sources current (drives ‘high’) until the voltage on the DTACK* line is approximately 1.5 V; then DTACK* goes to the

‘open-drain’ (high-impedance) state.

Figure 17. Reset Timing

Table 12. Asynchronous Timing Reference Parameters (Sheet 2 of 2)

Timing

No.

Figure

Parameter

MIN

MAX

Unit

VCC

CLK

RESET*

CLK/2

CD1283 Datasheet(PDF) 79 Page - Intel Corporation

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