CD1283 datasheet(22/94 Pages) INTEL

22 / 94 page

CD1283 — IEEE 1284-Compatible Parallel Interface

Datasheet

5.0

Functional Description

5.1

Device Architecture

The CD1283 consists of dedicated logic tailored to the function of sending and receiving parallel

data. The device implements an IEEE 1284-compliant parallel port with a specialized data pipeline

designed for high-speed transfers.

To maintain binary compatibility with the CD1284, much of the architectural layout has been

duplicated. Therefore, access to the register set of the parallel channel is only possible after loading

the AER with the CD1284 occupied parallel port address — namely channel 0. For all channel-

specific accesses, the CPU first loads the AER with a pointer to channel 0. Thereafter, all read and

write operations occur through the parallel channel.

The parallel channel is comprised of a FIFO and DMA data interface, as well as a high-speed state

machine to manage all modes defined in the IEEE Std 1284-1994 specification, Standard Signaling

Method for a Bidirectional Parallel Peripheral Interface for Personal Computers. The parallel port

performs the slave or peripheral function of the IEEE Std 1284 interface, and can accept

negotiations into any or all of the IEEE defined modes.

5.2

CPU Interface

The CPU interface is comprised of a 7-bit address bus, 8-bit bidirectional data bus, 16-bit DMA

port, and control inputs to identify the type of I/O cycle occurring. The signaling and basic timing

match that of the Motorola 68000 family. With the addition of minimal glue logic, the interface

will work with nearly any CPU. A special input is provided to swap the bytes on the data bus to

reduce the necessary logic needed with Intel-style CPUs.

The interface is completely compatible with the CD1284. Therefore, a CD1283 can be inserted into

a system in instead of a CD1284 and the parallel port operates without any modifications to the

CPU interface, parallel port hardware or software.

In most cases, when the CPU reads or writes an internal CD1283 location, it accesses a location in

a RAM array to serve as a bank of registers. However, some locations are mapped to actual

hardware resources. For example, when a hard output signal is required (such as a service-request

output in the SVRR) or a read of the actual state of an input is necessary (such as a parallel port

handshake signal in the IVR).

CD1283 Datasheet(PDF) 22 Page - Intel Corporation