CD1283 datasheet(42/94 Pages) INTEL

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CD1283 — IEEE 1284-Compatible Parallel Interface

Datasheet

5.8

General-Purpose I/O Port

The CD1283 provides an 8-bit general-purpose port (GP[7:0]) used to control or give status of

external functions. Each of the eight signals are individually programmable for direction, so the

port can be comprised of any number of inputs and outputs. Each port signal is implemented with a

standard, bidirectional HCMOS pad and is fully TTL compatible. The port is controlled through

two internal registers — GPDIR and GPIO.

Each bit in the GPDIR sets the direction of the corresponding bit in the GPIO; ‘1’ sets the signal as

output, and ‘0’ sets it as input. When writing to the GPIO, only the bits programmed as outputs are

affected by the contents of the data bus. When reading the GPIO, bits programmed as inputs reflect

the true state of the condition of the external pin; bits programmed as outputs reflect the state of the

last value written to the register and the current state of the output pins.

At reset, all bits in the GPIO are cleared and the signals are programmed as inputs.

Note:

Interrupts are not generated on signal changes within the General-Purpose I/O port; the CPU must

periodically poll GPIO to detect changes in external conditions. Therefore, if it is necessary to

detect changes, use the port with signals that change with low-duty cycles.

5.9

Parallel Port Interface

The CD1283 parallel port signals are implemented with Level-2 characteristics, as defined in the

IEEE Std 1284-1994 specification with the exception of transient protection. As such, the port can

be directly connected to the interface cable with the addition of a few external components. The

components consist of passive pull-up resistors, series impedance matching resistors, and clipping

diodes. Additional noise filtering may be required in an end system. Figure 10 illustrates a typical

interface with the components listed above.

Some system designs may require buffers between the CD1283 and the cable. Systems that require

drive cables longer than the specified maximum of 10 m or those that need to protect the CD1283

require inexpensive buffers between it and the cable. The device provides two signal outputs,

PDBEN and EBDIR, for connecting and controlling buffers (such as, 74AS245 or equivalent).

These signals do not allow direct control of the buffer. However, the addition of an XNOR gate

provides both an enable control signal and a signal to select the direction of the buffer. PDBEN and

EBDIR are outputs from the control state machine that indicate its current state (see Figure 11 on

page 44).

Table 7.

System Clock Setup

CLK Freq.

(MHz)

Time/Tic

(ns)

SPR Value

TP Width

62.5

500

520

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