CD1283 datasheet(84/94 Pages) INTEL

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CD1283 — IEEE 1284-Compatible Parallel Interface

Datasheet

8.3.2

Synchronous Timing

Use the following table as a reference to timing parameters of figures in this section.

Figure 24. Asynchronous DMA Write Cycle Timing

Figure 25. Asynchronous DMA Write Cycle Timing

t21

t24

t19

CLK

DMAACK*

DB[15:0]

MAY CHANGE

VALID

DMAREQ*

NOTE: This Figure 24 is still valid, however, Figure 25 illustrates a more robust timing.

DB[15:0]

DMAACK*

CLK

NOTE: The data is sampled on the third rising edge of CLK following the assertion of DMAACK*. If DMAACK* is held

active for more than three CLK cycles then the next DMA write cycle will simply be delayed, but the data will

still be sampled on the third rising CLK edge following the assertion of DMAACK*. If DMAACK* is active for

< 3

CLKs, the n the data is still sampled on the third rising CLK edge following the assertion of DMAACK*

(provided that DMAACK* is active long enough for the device to lastch it. Due to this somewhat synchronous

behavior, care must be taken to guarantee that the data is valid at this CLK edge. Do not assume that the data

will be sampled on the deassertion of DMAACK*.

t32

t29

VALID

DMAREQ*

t28

VALID

t31

t30

t32

t31

DMAACK* SYNCHRONIZED

HERE

DMAACK* SYNCHRONIZED

HERE

DATA SAMPLED

HERE

DATA SAMPLED

HERE

DMAACK* LATCHED

HERE

SEE NOTE

CD1283 Datasheet(PDF) 84 Page - Intel Corporation

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