CS5461 datasheet(14/46 Pages) CIRRUS

14 / 46 page

CS5461

DS546PP2

3.1 Theory of Operation

A computational flow diagram for the two data

paths is shown in Fig. 2. The analog waveforms at

the voltage/current channel inputs are subject to the

gains of the input PGAs. These waveforms are then

sampled by the delta-sigma modulators at a rate of

(MCLK/K) / 8.

3.1.1 High-Rate Digital Low-Pass Filters

The data is then low-pass filtered, to remove

high-frequency noise from the modulator output.

Referring to Figure 2, the high rate filters on both

channels are implemented as fixed Sinc3 filters.

Also note from Figure 2 that the digital data on the

voltage channel is subjected to a variable time-de-

lay filter. The delay depends on the value of the

seven phase compensation bits (see Phase Com-

pensation) set in the configuration register.

3.1.2 Digital Compensation Filters

The data from both channels is then passed through

two 4th-order IIR “compensation” filters, whose

purpose is to correct (compensate) for the magni-

tude roll-off of the low-pass filtering operation.

These filters “re-flatten” the magnitude response of

the I and V channels over the relevant frequency

range, by correcting for the magnitude roll-off ef-

fects that are induced onto the I and V signal spec-

trums by the Sinc3 low-pass filter stages.

3.1.3 Digital High-Pass Filters

Both channels provide an optional high-pass filter

(“HPF” in Figure 2) which can be engaged into the

signal path, in order to remove the DC content from

the current/voltage signal before the RMS/energy

calculations are made. These filters are activated by

enabling certain bits in the Configuration Register.

3.1.4 Gain and DC Offset Adjustment

After the filtering, the instantaneous voltage and

current digital codes are both subjected to value ad-

justments, based on the values in the DC Offset

Registers (additive) and the Gain Registers (multi-

plicative). These registers are used for calibration

of the device (see Section 4.4, Calibration). After

offset and gain, the data is available to the user by

reading the Instantaneous Voltage and Current

Registers.

3.1.5 Average (Real) Power Computation

The digital instantaneous voltage and current data

is then processed further. Referring to Figure 2, the

instantaneous voltage/current data samples are

multiplied together (one multiplication for each

pair of voltage/current samples) to form instanta-

neous power data. The instantaneous power data is

then averaged over N instantaneous conversions

(N = value in Cycle Count Register) to form the re-

sult in the Average Power Register. The average

power can be multiplied by the time duration of the

VOLTAGE

∆Σ

SINC 3

V *

CURRENT

SINC 3

DELAY

REG

DELAY

REG

HPF

Configuration Register *

PC[ 6:0] Bits

RMS

÷ N

out

dir

∆Σ

HPF

IIR

I *

P *

ACoff*

DCoff*

ACoff*

DCoff*

÷ N

PGA

IIR

÷ N

PulseRateE

* DENOTES REGISTER NAME

4th-order

TBC *

Energy -

to - Pulse

PulseRateF

out

Energy -

to - Pulse

off

Avg

Figure 2. Data Flow.

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