CS5461 datasheet(19/46 Pages) CIRRUS

19 / 46 page

CS5461

DS546PP2

be connected to their ground reference level. (See

Figure 5.)

If offset and gain calibration command bits are set,

only the offset calibration will be performed.

4.4.6 Description of Calibration Algorithms

The computational flow of the CS5461’s AC and

DC gain/offset calibration sequences are illustrated

in Figure 6. This figure applies to both the voltage

channel and the current channel.

Note:

For proper AC calibration, the value of the

Voltage/Current Gain Registers must be set to default

(1.0) before running the gain calibration(s), and the

value in the AC Offset Registers must be set to default

(0) before running calibrations. This can be

accomplished by a software or hardware reset of the

device. The values in the voltage/current calibration

registers do affect the results of the calibration

sequences.

4.4.6.1 AC Offset Calibration Sequence

The AC offset calibration obtains an offset value

that reflects the RMS output level when the inputs

are grounded. During normal operation, this AC

offset register value will be subtracted from each

successive voltage/current sample in order to nulli-

fy the AC offset that may be inherent in the signal

path.

4.4.6.2 DC Offset Calibration Sequence

The DC Offset Registers hold the negative of the

simple average of N samples taken while the DC

offset calibration was executed. The inputs should

be grounded during DC offset calibration. The DC

offset value is added to the signal path to nullify the

DC offset in the system.

4.4.6.3 AC Gain Calibration Sequence

The AC gain calibration algorithm attempts to ad-

just the Gain Register value such that the calibra-

tion reference signal level presented at the voltage

inputs will result in a value of 0.6 in the RMS Volt-

age Register. The rms level of the calibration signal

must be determined by the user. During AC voltage

gain calibration, the value in the RMS Voltage

age Gain Register.

Two examples of AC calibration and the resulting

shift in the digital output codes of the channel’s in-

stantaneous data registers are shown in Figures 7

and 8. Figure 8 shows that a positive (or negative)

DC level signal can be used even though an AC

gain calibration is being executed. However, an AC

signal cannot be used for DC gain calibration.

M odula to r

to V *, I*, P *, E * R e g is te rs

F ilte r

V RM S

SIN C

D C O ffse t*

Ga in *

-X

AC O ffset*

0.6

* Denotes readable/writable register

Figure 6. Calibration Data Flow

CS5461 Datasheet(PDF) 19 Page - Cirrus Logic

CS5461 Datasheet(HTML) 19 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Datasheet Download

Link URL