Electronic Components Datasheet Search
  English  ▼

X  

CS5461 Datasheet(PDF) 36 Page - Cirrus Logic

Part # CS5461
Description  Single Phase Bi-Directional Power/Energy IC
PDF  46 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5461 Datasheet(HTML) 36 Page - Cirrus Logic

Back Button CS5461 Datasheet HTML 32Page - Cirrus Logic CS5461 Datasheet HTML 33Page - Cirrus Logic CS5461 Datasheet HTML 34Page - Cirrus Logic CS5461 Datasheet HTML 35Page - Cirrus Logic CS5461 Datasheet HTML 36Page - Cirrus Logic CS5461 Datasheet HTML 37Page - Cirrus Logic CS5461 Datasheet HTML 38Page - Cirrus Logic CS5461 Datasheet HTML 39Page - Cirrus Logic CS5461 Datasheet HTML 40Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 36 / 46 page
background image
CS5461
36
DS546PP2
7.5 PulseRateE Register
Address: 6
Default** = 32000.00 Hz
The PulseRateE Register determines the average frequency of the pulses issued on the EOUT output pin. The
register’s smallest valid value is 2-4 but can be in 2-5 increments. A pulserate higher than MCLK/K/8 will result
in a pulse rate setting of MCLK/K/8.
7.6 I, V, P, & PAvg: Instantaneous Current, Voltage, Power, and Average Power (Signed)
Output Register
Address: 7 - 10
These signed registers contain the last measured value of I, V, P, and PAVG. The results will be within in the
range of -1.0
≤ I,V,P,PAvg< 1.0. The value is represented in two's complement notation, with the binary point
place to the right of the MSB (MSB has a negative weighting). These values are 22 bits in length. The two least
significant bits have no meaning, and will always have a value of “0”.
7.7 IRMS, VRMS Unsigned Output Register
Address: 11,12
These unsigned registers contain the last values of IRMS and VRMS. The results are in the range of
0.0
≤ I
RMS,VRMS < 1.0. The value is represented in (unsigned) binary notation, with the binary point place to the
left of the MSB. These results are updated after each computation cycle.
7.8 Timebase Calibration Register
Address: 13
Default** = 1.000
This register can be set with a clock frequency error compensation value, to correct for a gain/timing error
caused by the crystal/oscillator tolerance. The value is in the range 0.0
≤ TBC < 2.0.
MSB
LSB
218
217
216
215
214
213
212
211
.....
21
20
2-1
2-2
2-3
2-4
2-5
MSB
LSB
-(20)2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
MSB
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
.....
2-18
2-19
2-20
2-21
2-22
2-23
2-24
MSB
LSB
20
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com