CS5461 datasheet(22/46 Pages) CIRRUS

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CS5461

DS546PP2

4.8 On-Chip Temperature Sensor

After a few minutes of normal-active operation in

‘continuous conversions’ data acquisition mode,

the CS5461 will stabilize to a constant steady-state

operating temperature. However, the CS5461’s op-

erating temperature may be influenced by changes

in the ambient temperature. Such ambient temper-

ature fluctuations will cause some drift in the gain

of the CS5461’s two A/D converters. The on-chip

temperature sensor provides the option to calibrate

such drift.

The output code value in the Temperature Register

is the relative temperature reading of the on-chip

temperature sensor.

By recording the digitized temperature readings

and comparing these readings to the fluctuations in

the A/D output codes of the Vrms and Irms Regis-

ter readings, the fluctuation of the A/D converter

can be characterized over a wide range of ambient

temperatures.

Once a temperature drift characterization of the de-

vice has been performed, a temperature compensa-

tion algorithm can be integrated into the firmware

within the on-board MCU to compensate for this

temperature drift.

4.9 Interrupt

The INT pin is used to indicate that an event has

taken place in the converter that needs attention.

These events inform the system about operation

conditions and internal error conditions. The INT

signal is created by combining the Status Register

with the Mask Register. Whenever a bit in the Sta-

tus Register becomes active, and the corresponding

bit in the Mask Register is a logic 1, the INT signal

becomes active. The interrupt condition is cleared

when the bits of the Status Register are returned to

their inactive state.

4.9.1 Typical use of the INT pin

The steps below show how interrupts can be han-

dled.

•

Initialization:

Step I0 - All Status bits are cleared by writing

FFFFFF (Hex) into the Status Register.

Step I1 - The conditional bits which will be

used to generate interrupts are then set to

logic 1 in the Mask Register.

Step I3 - Enable interrupts.

•

Interrupt Handler Routine:

Step H0 - Read the Status Register.

Step H1 - Disable all interrupts.

Step H2 - Branch to the proper interrupt service

routine.

Step H3 - Clear the Status Register by writing

back the read value in step H0.

Step H4 - Re-enable interrupts.

Step H5 - Return from interrupt service routine.

This handshaking procedure insures that any

new interrupts activated between steps H0 and

H3 are not lost (cleared) by step H3.

4.9.2 INT Active State

The behavior of the INT pin is controlled by the

IMODE and IINV bits of the Configuration Regis-

ter. The pin can be active low (default), active high,

active on a return to logic 0 (pulse-low), or active

on a return to logic 1 (pulse-high). If the interrupt

output signal format is set for either pulse-high or

pulse-low, the duration of the INT pulse will be at

least one DCLK cycle (DCLK = MCLK / K).

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