MSM6789 datasheet(8/53 Pages) OKI

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MSM6789A/6789L

¡ Semiconductor

PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)

Symbol

Type

Description

Mode Selection.

Low level : Stand-alone mode

High level : Microcontroller interface mode

PDWN

Power Down. When a low level is input, the MSM6789A goes to the power down

state. Unlike the RESET pin, this pin does not force the MSM6789A to be reset.

When a Low level is applied to this pin during recording operation, the MSM6789A

is halted, and will be maintained in the power down state while PDWN is low level.

After this pin is restored to a high level, postprocessing for recording will be performed.

Oscillator Connection. When an external clock is used, input the clock through

this pin. During the power down state, this pin must be set to the ground level.

TEST

MSM6789A Test. Input a low level to the TEST pin and a high level to the TEST pin.

RSEL1

TEST

RSEL2

MSEL2

MSEL1

RSEL2

RSEL1

Memory capacity

LLLL

¥ 1

LLL

¥ 2

LHL

¥ 3

¥ 4

LHL

¥ 1

LHLH

¥ 2

¥ 3

HHH

¥ 4

• When serial register is selected (DRAM/SR = Low level)

MCUM

Oscillator Connection. When an external clock is used, this pin must be left

open.

MSM6789A Test. This pin must be left open.

TMD3-TMD0

TDT7-TDT0

SYNC

I/O

Connect these pins to DQ1-DQ4 of DRAM at the time of 4-bit

¥ type DRAM

selection. Otherwise these pins must be left open as they are MSM6789A test pins.

TDT3-TDT0

[DQ4]-[DQ1]

I/O

MSM6789A Test. Input a low level signal.

TST

TCK

TMD4

This pin selects CAS-before-RAS refresh period of DRAM at the time of

power down when DRAM is selected.

Low level : 15 µs max.

High level : 125 µs max.

LOWPWR

A high input level causes the MSM6789A to be initialized and to go into the power

down state.

RESET

9-12

17-20

13-20

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