UPD17P133CS datasheet(48/289 Pages) NEC

48 / 289 page

CHAPTER 5

DATA MEMORY (RAM)

5.1.4 Port Registers

A port register consists of five nibbles allocated at addresses 6FH to 73H in Bank0 of the data memory. As shown

in Figure 5-5, the two high-order bits of address 6FH are always set to 0.

Figure 5-5 shows the configuration of the port registers.

Figure 5-5. Port Register Configuration

Port Register

Address

6FH

70H

71H

72H

73H

P0E

P0A

P0B

P0C

P0D

PPPPPPPPPPPPPPPPPP

000000000000000000

AAAABBBBCCCC

DDDD

103210321032103210

5.1.5 General Data Memory

General data memory is all the data memory not used by the port and system registers (SYSREG). In other words,

general data memory consists of 64 nibbles (

µPD17120 and 17121) or 111 nibbles (µPD17132, 17133, 17P132, and

17P133).

5.1.6 Uninstalled Data Memory

There is no hardware installed at addresses 40H to 6EH of the

µPD17120 and 17121. Any attempt to read this

area will yield unpredictable results. Writing data to this area is invalid and should therefore not be attempted.

Figure 5-4. General Register (GR) Configuration

BANK0

Area specifiable as general register

0123456789

BANK0

Port register

Column address

SYSREG

General register

Pointed to by general register

pointer (RP) in system register.

Note that row addresses 4 to 6

in the case of the

PD17120

and 17121 are uninstalled mem-

ory locations. The register

pointer (RP) should therefore

not specify a row address in this

area.

UPD17P133CS Datasheet(PDF) 48 Page - NEC

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