AD4111 datasheet(32/59 Pages) AD

32 / 59 page

AD4111

Data Sheet

Rev. A | Page 32 of 59

SINGLE CYCLE SETTLING

The AD4111 can be configured by setting the SING_CYC bit in

the ADC mode register so that only fully settled data is output, thus

effectively putting the ADC into a single cycle settling mode. This

mode achieves single cycle settling by reducing the output data

rate to be equal to the settling time of the ADC for the selected

output data rate. This bit has no effect with the sinc5 + sinc1 filter

at output data rates of 2.6 kSPS and less or when multiple

channels are enabled.

Figure 44 shows a step on the analog input with single cycle

settling mode disabled and the sinc3 filter selected. The analog

input requires at least three cycles after the step change for the

output to reach the final settled value.

1/ODR

ANALOG

INPUT

FULLY

SETTLED

ADC

OUTPUT

Figure 44. Step Input Without Single Cycle Settling

Figure 45 shows the same step on the analog input but with

single cycle settling enabled. The analog input requires at least a

single cycle for the output to be fully settled. The output data

rate, as indicated by the RDY signal, is now reduced to equal the

settling time of the filter at the selected output data rate.

tSETTLE

ANALOG

INPUT

FULLY

SETTLED

ADC

OUTPUT

Figure 45. Step Input with Single Cycle Settling

ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS

The enhanced filters provide rejection of 50 Hz and 60 Hz

simultaneously and allow the user to trade off settling time and

rejection. These filters can operate at up to 27.27 SPS or can reject

up to 90 dB of 50 Hz ± 1 Hz and 60 Hz ± 1 Hz interference.

These filters are operated by postfiltering the output of the

sinc5 + sinc1 filter. For this reason, the sinc5 + sinc1 filter must

be selected when using the enhanced filters to achieve the

specified settling time and noise performance. Table 21 and

Table 22 show the output data rates with the accompanying

settling time, rejection, and rms noise. Figure 46 to Figure 53

show the frequency domain plots of the responses from the

enhanced filters.

Table 21. Enhanced Filters Output Data Rate, Voltage Input Noise, Settling Time, and Rejection Using the Enhanced Filters

Output Data Rate (SPS)

Settling

Time (ms)

Simultaneous Rejection of

50 Hz ± 1 Hz and 60 Hz ± 1 Hz (dB)1

Noise

(µV rms)

Peak-to-Peak

Resolution (Bits)

Comments

27.27

36.67

6.44

19.1

See Figure 46 and Figure 49

40.0

6.09

19.2

See Figure 47 and Figure 50

50.0

5.54

19.35

See Figure 48 and Figure 51

16.667

60.0

5.38

19.51

See Figure 52 and Figure 53

Master clock = 2.00 MHz.

Table 22. Enhanced Filters Output Data Rate, Current Input Noise, Settling Time, and Rejection Using the Enhanced Filters

Output Data Rate (SPS)

Settling

Time (ms)

Simultaneous Rejection of

50 Hz ± 1 Hz and 60 Hz ± 1 Hz (dB)1

Noise

(nA rms)

Peak-to-Peak

Resolution (Bits)

Comments

27.27

36.67

7.69

21.4

See Figure 46 and Figure 49

40.0

7.68

21.2

See Figure 47 and Figure 50

50.0

7.26

21.7

See Figure 48 and Figure 51

16.667

60.0

7.25

21.7

See Figure 52 and Figure 53

Master clock = 2.00 MHz.

AD4111 Datasheet(PDF) 32 Page - Analog Devices

AD4111 Datasheet(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL