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AD4111

Data Sheet

Rev. A | Page 52 of 59

GPIO CONFIGURATION REGISTER

Address: 0x06, Reset: 0x0800, Name: GPIOCON

The GPIO configuration register controls the general-purpose I/O pins of the ADC.

Table 30. Bit Descriptions for GPIOCON

Bits

Bit Name

Settings

Description

Reset

Access

[15:14]

Reserved

Reserved.

0x0

OP_EN0_1

GPO0/GPO1 output enable. This bit enables the GPO0 and GPO1 pins. The outputs

are referenced between AVDD and AVSS.

0x0

R/W

Disabled.

Enabled.

OW_EN

This bit enables the use of open wire detection of voltage channels.

0x0

R/W

Disabled.

Enabled.

SYNC_EN

SYNC input enable. This bit enables the SYNC pin as a sync input. When set low, the

SYNC pin holds the ADC and filter in reset until SYNC goes high. An alternative

operation of the SYNC pin is available when the ALT_SYNC bit in the interface mode

low on the SYNC pin does not immediately reset the filter/modulator. Instead, if the

SYNC pin is low when the channel is due to be switched, the modulator and filter are

prevented from starting a new conversion. Bringing SYNC high begins the next

conversion. This alternative sync mode allows SYNC to be used while cycling

through channels.

0x1

R/W

Disabled.

Enabled.

[10:9]

ERR_EN

Error pin mode. These bits enable the ERROR pin as an error input/output.

0x0

R/W

Disabled.

Enable error input (active low). ERROR is an error input. The (inverted) readback state

is OR'ed with other error sources and is available in the ADC_ERROR bit in the status

Enable open-drain error output (active low). ERROR is an open-drain error output.

The status register error bits are OR'ed, inverted, and mapped to the ERROR pin.

ERROR pins of multiple devices can be wired together to a common pull-up resistor

so that an error on any device can be observed.

General-purpose output (active low). ERROR is a general-purpose output. The status

of the pin is controlled by the ERR_DAT bit in this register. This output is referenced

between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the

GPIOx pins. The output has an active pull-up resistor in this case.

ERR_DAT

Error pin data. This bit determines the logic level at the ERROR pin if the pin is

enabled as a general-purpose output. This bit reflects the readback status of the pin

if the pin is enabled as an input.

0x0

R/W

Logic 0.

Logic 1.

GP_DATA1

GPO1 data. This bit is the write data for GPO1.

0x0

R/W

GPO1 = 0.

GPO1 = 1.

GP_DATA0

GPO0 data. This bit is the write data for GPO0.

0x0

R/W

GPO0 = 0.

GPO0 = 1.

[5:0]

Reserved

Reserved.

0x0

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