AD4111 datasheet(29/59 Pages) AD

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Data Sheet

AD4111

Rev. A | Page 29 of 59

DATA OUTPUT CODING

When the ADC is configured for unipolar operation, the output

code is natural (straight) binary with a zero differential input

voltage resulting in a code of 00 … 00, a midscale voltage

resulting in a code of 100 … 000, and a full-scale input voltage

resulting in a code of 111 … 111. The output code for any input

voltage is represented as

Code = (2N × VIN × 0.1)/VREF

The output code for any input current is represented as

Code = (2N × IIN × 50 Ω)/VREF

When the ADC is configured for bipolar operation, the output

code is offset binary with a negative full-scale voltage resulting

in a code of 000 … 000, a zero differential input voltage resulting in

a code of 100 … 000, and a positive full-scale input voltage

resulting in a code of 111 … 111. The output code for any

analog input voltage can be represented as

Code = 2N –1 × ((VIN × 0.1/VREF) + 1)

The output code for any input current is represented as

Code = 2N− 1 × ((IIN × 50 Ω/VREF) + 1)

where:

N = 24.

VIN is the input voltage.

IIN is the input current.

VREF is the reference voltage.

AD4111 REFERENCE

The AD4111 offers the user the option of either supplying an

external reference to the REF+ and REF− pins of the device,

using AVDD – AVSS, or by allowing the use of the internal

2.5 V, low noise, low drift reference. Select the reference source

to be used by the analog input by setting the REF_SELx bits,

Bits[5:4], in the setup configuration registers appropriately. The

structure of the Setup Configuration 0 register is shown in Table 19.

By default, the AD4111 uses an external reference on power-up.

Internal Reference

The AD4111 includes a low noise, low drift voltage reference.

The internal reference has a 2.5 V output. The internal reference

is output on the REFOUT pin after the REF_EN bit in the ADC

mode register is set and is decoupled to AVSS with a 0.1 μF

capacitor. The AD4111 internal reference is disabled by default

on power-up.

External Reference

The AD4111 has a fully differential reference input applied

through the REF+ and REF− pins. Standard low noise, low drift

voltage references, such as the ADR4525, are recommended for

use. Apply the external reference to the AD4111 reference pins

as shown in Figure 39. Decouple the output of any external

reference to AVSS. As shown in Figure 39, the ADR4525 output

is decoupled with a 0.1 μF capacitor at the output for stability

purposes. The output is then connected to a 4.7 μF capacitor,

which acts as a reservoir for any dynamic charge required by the

ADC, and is followed by a 0.1 μF decoupling capacitor at the

REF+ input. This capacitor is placed as close as possible to the

REF+ and REF− pins.

The REF− pin is connected directly to the AVSS potential. When

an external reference is used instead of the internal reference

to supply the AD4111, attention must be paid to the output of

the REFOUT pin. The internal reference is controlled by the

REF_EN bit (Bit 15) in the ADC mode register, which is shown

in Table 20. If the internal reference is not being used elsewhere

in the application, ensure that the REF_EN bit is disabled.

2.5V VREF

0.1µF

ADR4525

3V TO 18V

0.1µF

4.7µF

AD4111

REF+

REF–

1ALL DECOUPLING IS TO AVSS.

2ANY OF THE ADR4525 FAMILY REFERENCES CAN BE USED.

ADR4525 ENABLES REUSE OF THE 3.3V ANALOG SUPPLY

NEEDED FOR AVDD TO POWER THE REFERENCE VIN.

Figure 39. ADR4525 Connected to AD4111 REF± Pins

Table 19. Setup Configuration 0 Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x20

SETUPCON0

[15:8]

Reserved

BI_UNIPOLAR0

REFBUF0+

REFBUF0−

INBUF0

0x1000

[7:0]

Reserved

REF_SEL0

Reserved

Table 20. ADC Mode Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x01

ADCMODE

[15:8]

REF_EN

Reserved

SING_CYC

Reserved

Delay

0x2000

[7:0]

Reserved

Mode

CLOCKSEL

Reserved

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