AD4112 datasheet(11/58 Pages) AD

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Data Sheet

AD4112

Rev. A | Page 11 of 58

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VINCOM

VIN0

VIN1

VIN2

VIN3

REFOUT

REGCAPA

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT ANYTHING TO THIS PIN.

PIN 24 IS INTERNALLY CONNECTED TO AVSS.

2. SOLDER THE EXPOSED PAD TO A SIMILAR PAD ON THE PCB UNDER THE

EXPOSED PAD TO CONFER MECHANICAL STRENGTH AND FOR HEAT

DISSIPATION. THE EXPOSED PAD MUST BE CONNECTED TO AVSS

THROUGH THIS PAD ON THE PCB.

AVSS

AVDD

DNC

23 DNC

24 DNC

25 GPO0

26 VIN4

27 VIN5

28 VIN6

29 VIN7

30 IIN3–

22 REGCAPD

21 DGND

TOP VIEW

(Not to Scale)

AD4112

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic1

Type2

Description

VINCOM

Voltage Input Common. Voltage inputs are referenced to this pin when configured as single-ended.

Connect this pin to analog ground.

VIN0

Voltage Input 0. Input referenced to VINCOM in single ended configuration, or a positive input of an

input pair with VIN1 in differential configuration.

VIN1

Voltage Input 1. Input referenced to VINCOM in single ended configuration, or a negative input of an

input pair with VIN0 in differential configuration.

VIN2

Voltage Input 2. Input referenced to VINCOM in single ended configuration, or a positive input of an

input pair with VIN3 in differential configuration.

VIN3

Voltage Input 3. Input referenced to VINCOM in single ended configuration, or a negative input of an

input pair with VIN2 in differential configuration.

REFOUT

Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS. Decouple this pin to

AVSS using a 0.1 µF capacitor.

REGCAPA

Analog Low Dropout (LDO) Regulator Output. Decouple this pin to AVSS using a 1 µF capacitor and a

0.1 µF capacitor.

AVSS

Negative Analog Supply. This supply ranges from −2.75 V to 0 V and is nominally set to 0 V.

AVDD

Analog Supply Voltage. This voltage ranges from 3.0 V to 5.5 V with respect to AVSS.

DNC

N/A

Do Not Connect. Do not connect anything to this pin.

VBIAS−

Voltage Bias Negative. The pin is setting bias voltage for the voltage input analog front-end. Connect

this pin to AVSS.

XTAL1

Input 1 for Crystal.

XTAL2/CLKIO

AI/DI

Input 2 for Crystal/Clock Input or Output. See the CLOCKSEL bit settings in the ADCMODE register for

more information.

DOUT/RDY

Serial Data Output/Data Ready Output. This pin serves a dual purpose. It functions as a serial data

output pin to access the output shift register of the ADC. The output shift register can contain data from

any of the on-chip data or control registers. The data-word/control word information is placed on the

DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY

output is tristated. When CS is low, and a register is not being read, DOUT/RDY operates as a data ready

pin, going low to indicate the completion of a conversion. If the data is not read after the conversion,

the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an

interrupt to a processor, indicating that valid data is available.

DIN

Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the

control registers in the ADC, with the register address (RA) bits of the communications register

identifying the appropriate register. Data is clocked in on the rising edge of SCLK.

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