AD4112 datasheet(29/58 Pages) AD

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Data Sheet

AD4112

Rev. A | Page 29 of 58

BUFFERED REFERENCE INPUT

The AD4112 has true rail-to-rail, integrated, precision unity

gain buffers on both ADC reference inputs. The buffers provide

the benefit of providing high input impedance and allowing

high impedance external sources to be directly connected to the

reference inputs. The integrated reference buffers can fully drive

the internal reference switch capacitor sampling network,

simplifying the reference circuit requirements. Each reference

input buffer amplifier is fully chopped, meaning that it minimizes

the offset error drift and 1/f noise of the buffer. When using a

reference, such as the ADR4525, these buffers are not required

because these references, with proper decoupling, can drive the

reference inputs directly.

CLOCK SOURCE

The AD4112 uses a nominal master clock of 2 MHz. The AD4112

can source its sampling clock from one of three sources:

•

An internal oscillator.

•

An external crystal (use a 16 MHz crystal automatically

divided internally to set the 2 MHz clock).

•

An external clock source.

All output data rates listed in the data sheet relate to a master

clock rate of 2 MHz. Using a lower clock frequency from, for

instance, an external source scales any listed data rate propor-

tionally. To achieve the specified data rates, particularly rates for

rejection of 50 Hz and 60 Hz, use a 2 MHz clock. The source of

the master clock is selected by setting the CLOCKSEL bits

(Bits[3:2]) in the ADC mode register, as shown in Table 20. The

default operation on power-up and reset of the AD4112 is to

operate with the internal oscillator. It is possible to fine tune the

output data rate and filter notch at low output data rates using

the SINC3_MAPx bits.

Internal Oscillator

The internal oscillator runs at 16 MHz and is internally divided

down to 2 MHz for the modulator and can be used as the ADC

master clock. The internal oscillator is the default clock source for

the AD4112 and is specified with an accuracy of −2.5% to +2.5%.

There is an option to allow the internal clock oscillator to be output

on the XTAL2/CLKIO pin. The clock output is driven to the

IOVDD logic level. This option can affect the dc performance of

the AD4112 due to the disturbance introduced by the output

driver. The extent to which the performance is affected depends

on the IOVDD voltage supply. Higher IOVDD voltages create a

wider logic output swing from the driver and affect performance

to a greater extent. This effect is further exaggerated if the

IOSTRENGTH bit is set at higher IOVDD levels (see Table 27

for more information).

External Crystal

If higher precision, lower jitter clock sources are required, the

AD4112 can use an external crystal to generate the master clock.

The crystal is connected to the XTAL1 and XTAL2/CLKIO pins.

A recommended crystal for use is the FA-20H, a 16 MHz,

10 ppm, 9 pF crystal from Epson-Toyocom that is available in a

surface-mount package. As shown in Figure 40, insert two

capacitors (CX1 and CX2) from the traces connecting the

crystal to the XTAL1 and XTAL2/CLKIO pins. These capacitors

allow circuit tuning. Connect these capacitors to the DGND pin.

The value for these capacitors depends on the length and

capacitance of the trace connections between the crystal and the

XTAL1 and XTAL2/CLKIO pins. Therefore, the values of these

capacitors differ depending on the PCB layout and the crystal

used.

AD4112

XTAL1

CX1

1DECOUPLE TO DGND

CX2

XTAL2/CLKIO

Figure 40. External Crystal Connections

The external crystal circuitry can be sensitive to the SCLK

edges, depending on the SCLK frequency, IOVDD voltage,

crystal circuitry layout, and the crystal used. During crystal startup,

any disturbances caused by the SLCK edges may cause double

edges on the crystal input, resulting in invalid conversions until

the crystal voltage has reached a high enough level such that

any interference from the SCLK edges is insufficient to cause

double clocking. This double clocking can be avoided by

ensuring that the crystal circuitry has reached a sufficient

voltage level after startup before applying any SCLK.

Because of the nature of the crystal circuitry, it is recommended

that empirical testing of the circuit be performed under the

required conditions, with the final PCB layout and crystal, to

ensure correct operation.

External Clock

The AD4112 can also use an externally supplied clock. In

systems where an externally supplied clock is used, the external

clock is routed to the XTAL2/CLKIO pin. In this configuration,

the XTAL2/ CLKIO pin accepts the externally sourced clock

and routes it to the modulator. The logic level of this clock input

is defined by the voltage applied to the IOVDD pin.

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