9

PS/2 Mode Output Waveforms @ 24 MHz

Host Sending Data Timing Diagram

Notes:

1. The mouse checks the DATA line. If the line is low, the system has data to transmit. The DATA line is set inactive when the start bit (always 0) is

placed on the DATA line.

2. The mouse samples the DATA line for each bit while the CLK line is high. Data must be stable within 1 microsecond after the rising edge of the

CLK line.

3. The mouse checks for a high stop bit after the 10th CLK. If the DATA line is low, the mouse continues to clock until the DATA line becomes high,

then clocks the line-control bit, and at the next opportunity sends a Resend command to the system.

4. The mouse pulls the DATA line low, producing the line-control bit.

5. The host can pull the CLK line low, inhibiting the mouse.

Timing Parameter

Description

Min. Time

Max. Time

T1

Duration of CLK high

22.5

µsec

37.5

µsec

T2

Duration of CLK low

22.5

µsec

37.5

µsec

T3

Time from falling CLK transition, to date transition

0

µsec

22.5

µsec

Host Receiving Timing Diagram

Notes:

1. The host can hold the clock signal low to inhibit the next transmission.

2. The host raises the clock line to allow the next transmission.

3. All times given below assume a 24 MHz resonator and are dependent upon its accuracy.

Timing Parameter

Description

Min. Time

Max. Time

T1

Time from DATA transition to falling edge of CLK

3.75

µsec

18.75

µsec

T2

Time from rising edge of CLK to DATA transition

3.75

µsec

18.75

µsec

T3

Duration of CLK low

22.5

µsec

37.5

µsec

T4

Duration of CLK high

22.5

µsec

37.5

µsec

T5

Time to mouse inhibit after clock 11 to ensure the

0

µsec

37.5

µsec

mouse does not start another transmission

T1

T2

T3

CLK

I/O

INHIBIT

1ST

CLK

2ND

CLK

9TH

CLK

10TH

CLK

11TH

CLK

(5)

DATA

START BIT

(1)

(2)

(2)

(4)

BIT 0

PARITY BIT

STOP

BIT

(3)

T3

T4

T2

CLK

1ST

CLK

2ND

CLK

3RD

CLK

10TH

CLK

11TH

CLK

(1, 2)

DATA

START BIT

BIT 0

BIT 2

T1

BIT 1

PARITY BIT

STOP BIT

T5