LTC2964 datasheet(11/20 Pages) AD

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LTC2962/LTC2963/LTC2964

Rev 0

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OPERATION

The LTC2962 family monitors up to four power supplies

(or channels) with industry leading ±0.5% accuracy over

a wide temperature range. While primarily intended for

monitoring undervoltage (UV) events, the LTC2962 family

has a mode allowing for overvoltage (OV) monitoring. In

typical operation, if any of the monitored supplies fall below

a predetermined threshold, the reset output, RST, pulls

low immediately. When all four supplies rise above their

threshold (or below, in the case of –ADJ mode), the reset

output is released after a timeout period. The reset timeout

can be a fixed 200ms or it can be adjusted using an external

capacitor. The reset output is held low during power-up,

power-down and brownout conditions on any channel.

±ADJ modes and fourteen UV thresholds can be con-

figured for each channel individually. Each of the four

program (PG) inputs select one of sixteen voltage monitor

thresholds for each input respectively. During power-up,

a 4-bit ADC converts the voltage on each PG input. The

resultant digital value is decoded into one of the sixteen

threshold options (see Table 1). This technique allows

for 1% standard resistors to be used to configure the PG

inputs while maintaining tight ±0.5% accuracy for each

threshold. 65,536 different threshold combinations can

be selected with the LTC2962 family, including the ability

to monitor the same voltage on more than one channel.

The +ADJ and –ADJ modes compare the channel inputs

to 0.5V. With an external resistive divider, +ADJ can be

used to monitor any voltage greater than 0.5V. –ADJ can

be used as an overvoltage monitor for positive supplies

or an undervoltage monitor for negative supplies.

The reset disable function, RDIS, eases system voltage

margining by forcing RST high. During normal operation,

RST will go low when the monitored voltage (e.g. V1, V2,

etc.) falls below its threshold (or above, in the case of –

ADJ mode). By disabling the reset function with RDIS, a

microprocessor voltage limit can be tested through mar-

gining without issuing a system reset. In addition to being

able to ignore valid reset outputs, a manual reset can also

be commanded with the MR input. This input has an inter-

nal pull-up and debounce circuitry making it well suited

for a pushbutton input. When MR goes low, RST pulls low

immediately. When MR goes high, RST is released after

the configured reset timeout delay – assuming that all four

monitored voltages are above their configured threshold.

With DVCC grounded, RST is an open-drain output weakly

pulled up internally to VCC by 6µA through a Schottky

diode. However, if DVCC is externally connected to a volt-

age greater than 1.6V, then RST will be driven as an active

push-pull output to DVCC.

LTC2963 Watchdog Functionality

In addition to the common LTC2962 family functionality

discussed above, the LTC2963 offers a watchdog func-

tion. In the LTC2963, the WDI input must receive an edge

(rising or falling) at least as often as the configured watch-

dog upper timeout period. This time can be fixed to 1.6s

by connecting WT to VCC or it can be adjusted using an

external capacitor on WT. If WDI does not receive a signal

quickly enough, then WDO (watchdog status) and RST

outputs will both pull low. RST returns high after a single

reset timeout period. Like the RST output, the WDO output

has a weak internal pull-up to VCC, but can be used as an

active push-pull if DVCC is greater than 1.6V. The details

of WDO functionality can be found in the Watchdog Timer

section.

Following a reset event, the microprocessor under super-

vision may require more time than usual to send valid

watchdog edge transitions. The 3-state WDS input pro-

vides a way to choose three different initial watchdog

timeout periods immediately following a reset.

LTC2964 Individual Outputs

The LTC2964 provides individual comparator outputs for

each voltage input. These outputs could serve as a status

indicator, e.g. power good, or be part of a power supply

sequencer circuit. OUT1 through OUT4 provide the out-

puts of each of the four channel comparators without the

adjustable reset timeout delay.

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