LTC2964 datasheet(13/20 Pages) AD

13 / 20 page

LTC2962/LTC2963/LTC2964

Rev 0

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APPLICATIONS INFORMATION

First, create a resistive divider between REF and GND

composed of fifteen ideal 10k resistors. For a specific

input threshold combination, locate the optimal tap point

for each PG input following the ratio provided in Table 1.

Second, merge all resistors between any two adjacent tap

points into one single resistor and choose the standard

value using Table 2. Note the actual resistors in Table 2

are standard 1% values. Despite the difference between

the actual and the calculated resistance value as well as

the 1% tolerance, the LTC2962 family is guaranteed to

select the proper configuration.

Table 1. Voltage Configuration Table

SUPPLY VOLTAGE

OPTIMAL RATIO VPG/VREF

+ADJ

5.0V, –4%

14/15

5.0V, –6%

13/15

3.3V, –4%

12/15

3.3V, –6%

11/15

2.5V, –4%

10/15

2.5V, –6%

9/15

1.8V, –4%

8/15

1.8V, –6%

7/15

1.5V, –4%

6/15

1.5V, –6%

5/15

1.2V, –4%

4/15

1.2V, –6%

3/15

1.0V, –4%

2/15

1.0V, –6%

1/15

–ADJ

Figure 3 shows an example of choosing PG resistors

using the above procedure. In the example, the V1 moni-

tor threshold is 5V –4% (4.8V), V2 is 3.3V –6% (3.102V),

V3 is 1.2V –4% (1.152V) and V4 is set to –ADJ mode,

respectively.

When a DAC is used to drive the PG inputs, the LTC2962

family is guaranteed to operate properly for bias voltage

within ±1.5% of VREF relative to the optimal value.

During power-up, once VCC reaches VCCMINC (2.2V max),

the LTC2962 family enters a configuration period of

approximately 500µs during which the voltage on each

of the four PG inputs are sampled and the monitor is

configured to the desired threshold. Immediately after

configuration, the comparators are enabled and supply

monitoring will begin. Note once the part is configured,

it cannot be reconfigured without powering down. Do not

add capacitance to the PG inputs. It is always benefi-

cial to Kelvin connect the resistive divider ground to the

LTC2962 family GND.

Table 2. Recommended 1% Resistors for Programming

CALCULATED RESISTOR VALUE

(kΩ)

ACTUAL RESISTOR VALUE

(kΩ)

30.1

40.2

49.9

60.4

69.8

80.6

90.9

100

110

120

121

130

140

Figure 2. Monitor Configuration

Figure 3. Programming (PG) Pin Bias Example

LTC2962

FAMILY

REF

296234 F02

PGn

GND

RX4

10k

REF

296234 F03

RX3

30.1k

RX2

69.8k

RX1

40.2k

PG1

PG2

PG3

PG4

STEP 1: IDEAL LADDER

STEP 2: CHOOSE ACTUAL

RESISTORS

R14

10k

REF

R13

10k

R12

10k

PG1

–4%

PG4

–ADJ

PG3

1.2V

–4%

PG2

3.3V

–4%

10k

R10

10k

R11

10k

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