LTC4376 datasheet(7/16 Pages) AD

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LTC4376

Rev 0

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Figure 1a.

4376 F01a

INK

SHDN

OUT

OUTK

VSS

LTC4376

SMAJ24CA

24V

COUT

47nF

VOUT

12V

VIN

12V

12V/7A Ideal Diode with Reverse Input Protection

Figure 1b.

4376 F01b

INK

SHDN

OUT

OUTK

VSS

LTC4376

COUT

100µF

VOUT

12V

VIN

12V

SBR1U150SA

12V/7A Ideal Diode without Reverse Input Protection

Shutdown Mode

In shutdown, the LTC4376 pulls GATE low to CS, turning

off the internal MOSFET and reducing its current consump-

tion to 9µA. Shutdown does not interrupt forward current

flow, a path is still present through the internal MOSFET’s

body diode. A second external MOSFET is needed to block

the forward path; see the section Load Switching and

Inrush Control. When enabled, the LTC4376 operates as

an ideal diode. If shutdown is not needed, connect SHDN

to IN. SHDN may be driven with a 3.3V or 5V logic signal

or pulled up with an external resistor to IN. To enable

the part, SHDN must be pulled up to at least 2V. Use

a resistor value that provides more than the SHDN pin

leakage current of 1µA at 2.6V. A value of 1MΩ or less

is sufficient to turn the part on. To assert SHDN low, the

pull-down must sink at least 5µA plus the current pro-

vided by the external pull-up resistor at 500mV. When a

high impedance pull-up resistor is used, SHDN is subject

to capacitive coupling from nearby clock lines or traces

exhibiting high dV/dt. Bypass SHDN to VSS with 10nF to

eliminate injection. Figure 2 is the simplest way to control

the shutdown pin. Since the control signal ground is dif-

ferent from the SHDN pin reference, VSS, there could be

momentary glitches on SHDN during transients. Figure 3

APPLICATIONS INFORMATION

and Figure 4 are alternative solutions that level-shift the

control signal and eliminate glitches.

Figure 2.

OFF

4376 F02

SHDN

VSS

LTC4376

BSS123

SHDN Control

Figure 3.

OFF

4376 F03

SHDN

VSS

LTC4376

2N5551

24V

2N5401

240k

100k

240k

100k

Transistor SHDN Control

Figure 4.

OFF

4376 F04

SHDN

VSS

LTC4376

24V

MOC

207M

Opto-Isolator SHDN Control

Input Short-Circuit Faults

The dynamic behavior of an active, ideal diode entering

reverse bias is most accurately characterized by a delay

followed by a period of reverse recovery. During the delay

phase some reverse current is built up, limited by parasitic

resistances and inductances. During the reverse recovery

phase, energy stored in the parasitic inductances is trans-

ferred to other elements in the circuit. Current slew rates

during reverse recovery may reach 100A/µs or higher.

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