LTC4376

8

Rev 0

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APPLICATIONS INFORMATION

High slew rates coupled with parasitic inductances in

series with the input and output paths may cause poten-

tially destructive transients to appear at the IN, CS and

OUT pins of the LTC4376 during reverse recovery. A zero

impedance short-circuit directly across the input and

ground is especially troublesome because it permits the

highest possible reverse current to build up during the

delay phase. When the internal MOSFET finally turns off

to interrupt the reverse current, the LTC4376 IN and CS

pins experience a negative voltage spike while the OUT

pin spikes in the positive direction.

To prevent damage to the LTC4376 under conditions of

input short-circuit, protect the IN, CS and OUT pins as

shown in Figure 5. The IN and CS pins are protected by

voltages 24V and greater, D3 is needed to protect the inter-

nal MOSFET’s gate oxide during input short-circuit condi-

tions. Negative spikes, seen after the MOSFET turns off

during an input short, are clamped by D2, a 24V TVS. D2

allows reverse inputs to 24V while keeping the MOSFET

off and is not required if reverse input protection is not

needed. D1 blocks D2 from conducting during normal

operation. When the input short condition disappears,

flows through the body diode of the MOSFET charging

CS and OUT pins may rise to a level that can damage

the LTC4376. In this case, D1 will need to be a TVS or

TransZorb to limit the voltage difference between the IN/

OUT is protected by the MOSFET’s avalanche breakdown.

Nevertheless, the MOSFET could be damaged by exces-

sive current in applications greater than 24V. If the input

is greater than 24V, then a 28V TVS (SMAJ28A) or a snub-

ber can be used to protect the MOSFET and OUT pin. The

snubber allows applications up to 40V (see Figure 13).

parasitic inductance causes the IN and OUT voltages to

drop quickly.

Paralleling Supplies

Multiple LTC4376s can be used to combine the outputs of

two or more supplies for redundancy or for droop sharing,

as shown in Figure 6. For redundant supplies, the supply

with the highest output voltage sources most or all of the

load current. If this supply’s output is quickly shorted to

ground while delivering load current, the flow of current

temporarily reverses and flows backwards through the

LTC4376’s internal MOSFET. The LTC4376 senses this

reverse current and activates a fast pull-down to quickly

turn off the MOSFET.

If the other, initially lower supply was not delivering any

load current at the time of the fault, the output falls until

the body diode of its ORing internal MOSFET conducts.

Meanwhile, the LTC4376 charges the internal MOSFET

gate with 10µA until the forward drop is reduced to 30mV.

If this supply was sharing load current at the time of the

fault, its associated ORing internal MOSFET was already

driven partially on. In this case, the LTC4376 will simply

Figure 5.

D4*

SMAJ28A

4376 F05

IN

CS

GATE

INK

SHDN

OUT

OUTK

LTC4376

D2

SMAJ24A

24V

D1

1N4148

D3

DDZ9699T

12V

>1.5µF

R1

1k

OUTPUT PARASITIC

INDUCTANCE

REVERSE

RECOVERY CURRENT

INPUT

SHORT

INPUT PARASITIC

INDUCTANCE

SOURCE PARASITIC

INDUCTANCE

Reverse Recovery Produces Inductive Spikes at the IN, CS and OUT Pins. The Polarity of

Step Recovery Is Shown Across Parasitic Inductances