ADS7028 datasheet(12/70 Pages) TI1

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AVDD

LSB

tAVG = N samples x tCYCLE

Sample

AINx

(start of averaging)

Sample

AINx

SCLK

Sample

AINx

[15:0] Data

SDO

16 clocks

N ± 1 conversions triggered

internally

ADS7038

SBAS979 – JUNE 2019

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8.3.5 Programmable Averaging Filter

The ADS7038 features a built-in oversampling (OSR) function that can be used to average several samples. The

averaging filter can be enabled by programming the OSR[2:0] bits in the OSR_CFG register. The averaging filter

configuration is common to all analog input channels. Figure 5 shows that the averaging filter module output is

16 bits long. In manual conversion mode and auto-sequence mode, only the first conversion for the selected

analog input channel must be initiated by the host; see the Manual Mode and Auto-Sequence Mode sections. As

shown in Figure 5, any remaining conversions for the selected averaging factor are generated internally. The

time required to complete the averaging operation is determined by the sampling speed and number of samples

to be averaged. As shown in Figure 5, the 16-bit result can be read out after the averaging operation completes.

Figure 5. Averaging Example

In autonomous mode of operation, samples from analog input channels that are enabled in the

AUTO_SEQ_CH_SEL register are averaged sequentially. The digital window comparator compares the top 12

bits of the 16-bit average result with the thresholds.

Equation 2 provides the LSB value of the 16-bit average result.

(2)

8.3.6 CRC on Data Interface

The ADS7038 features a cyclic redundancy check (CRC) module for checking the integrity of the data bits

exchanged over the SPI interface. The CRC module is bidirectional, which appends an 8-bit CRC to every byte

read from the device and also evaluates the CRC of every incoming byte over the SPI interface. The CRC

module uses the CRC-8-CCITT polynomial (x8 + x2 + x + 1) for CRC computation.

To enable the CRC module, set the CRC_EN bit in the GENERAL_CFG register. Table 2 shows the different

ways that a CRC error that occurs when configuring the ADS7038 can be detected.

Table 2. Configuring Notifications when CRC Error is Detected

CRC ERROR NOTIFICATION

CONFIGURATION

DESCRIPTION

ALERT

ALERT_CRCIN = 1b

ALERT (internal signal) is asserted if a CRC error is detected

Status flags

APPEND_STATUS = 10b

4-bit status flags are appended to the ADC data. See the Output Data

Format section for details.

—

Read the CRCERR_IN bit to check if a CRC error was detected.

ADS7028 Datasheet(PDF) 12 Page - Texas Instruments

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