ADS7028 datasheet(13/70 Pages) TI1

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ADS7038

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SBAS979 – JUNE 2019

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When the ADS7038 detects a CRC error on the SPI interface, the erroneous data are ignored and the

CRCERR_IN bit is set. Additional notifications can be enabled as described in Table 2. Further register writes are

disabled until the CRCERR_IN bit is cleared by writing 1b to this bit. When using autonomous conversion mode,

further conversions can be disabled on a CRC error on the SPI interface by setting CONV_ON_ERR = 1b.

8.3.7 General-Purpose I/Os

The eight channels of the ADS7038 can be independently configured as analog inputs, digital inputs, or digital

outputs. Table 3 shows how the PIN_CFG and GPIO_CFG registers can be used to configure the device

channels.

Table 3. Configuring Channels as Analog Inputs or GPIOs

PIN_CFG[7:0]

GPIO_CFG[7:0]

GPO_DRIVE_CFG[7:0]

CHANNEL CONFIGURATION

Analog input (default)

Digital input

Digital output; open-drain driver

Digital output; push-pull driver

Digital outputs can be configured to logic 1 or 0 by writing to the GPO_OUTPUT_VALUE register. Reading the

GPI_VALUE register returns the logic level for all channels configured as digital inputs or digital outputs. The

GPI_VALUE register can be read to detect a failure in external components, such as a floating pullup resistor or

a low-impedance pulldown resistor, that prevents digital outputs being set to the desired logic level.

8.3.8 Oscillator and Timing Control

The device uses an internal oscillator for conversion. When using the averaging module, the host initiates the

first conversion and subsequent conversions are generated internally by the device. Table 4 describes how the

sampling rate can be controlled by the OSC_SEL and CLK_DIV[3:0] register fields when the device generates

the start of the conversion.

Table 4. Configuring Sampling Rate for Internal Conversion Start Control

CLK_DIV[3:0]

OSC_SEL = 0

OSC_SEL = 1

SAMPLING FREQUENCY, fCYCLE

(kSPS)

CYCLE TIME,

tCYCLE (µs)

SAMPLING FREQUENCY,

fCYCLE (kSPS)

CYCLE TIME, tCYCLE

(µs)

0000b

1000

31.25

0001b

666.7

1.5

20.83

0010b

500

15.63

0011b

333.3

10.42

0100b

250

7.81

128

0101b

166.7

5.21

192

0110b

125

3.91

256

0111b

2.60

384

1000b

62.5

1.95

512

1001b

41.7

1.3

768

1010b

31.3

0.98

1024

1011b

20.8

0.65

1536

1100b

15.6

0.49

2048

1101b

10.4

0.33

3072

The conversion time of the device, given by tCONV in the Switching Characteristics table, is independent of the

OSC_SEL and CLK_DIV[3:0] configuration.

ADS7028 Datasheet(PDF) 13 Page - Texas Instruments

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